Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path
A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path. The command address input circuit includes a counter that stores and increments the row address. The system also includes a flip-flop that stores the row address in response to receiving a command to refresh the first set of memory banks.
1. A system comprising:
a plurality of memory banks configured to store data, wherein the plurality of memory banks comprises a first set of memory banks and a second set of memory banks;
an address path coupled to the plurality of memory banks, wherein the address path is configured to provide a row address to the plurality of memory banks; and
a command address input circuit coupled to the address path, wherein the command address input circuit comprises:
a counter configured to store and increment the row address; and
a flip-flop configured to store the row address incremented by the counter in response to receiving a command to refresh the first set of memory banks, wherein the command address input circuit is configured to select the row address stored in the flip-flop and refresh a first row of the first set of memory banks associated with the row address stored in the flip-flop via the address path while activating a second row of the second set of memory banks via the address path.
2. The system of claim 1 , wherein the command address input circuit is configured to select the row address stored in the counter and refresh a row of the plurality of memory banks associated with the row address stored in the counter via the address path when the plurality of memory banks is synchronized.
3. The system of claim 1 , wherein the command address input circuit is configured to select the row address stored in the flip-flop and refresh a row of the plurality of memory banks associated with the row address stored in the flip-flop via the address path when the plurality of memory banks is unsynchronized.
4. The system of claim 3 , wherein the plurality of memory banks remains unsynchronized after the command address input circuit refreshes the row of the plurality of memory banks associated with the row address stored in the flip-flop.
5. The system of claim 1 , wherein the command address input circuit is configured to select the row address stored in the flip-flop and refresh a row of the first set of memory banks associated with the row address stored in the flip-flop via the address path when the plurality of memory banks is unsynchronized.
6. The system of claim 5 , wherein the plurality of memory banks remains unsynchronized after the command address input circuit refreshes the row of the first set of memory banks associated with the row address stored in the flip-flop.
7. The system of claim 1 , wherein the command address input circuit is configured to select the row address stored in the flip-flop and refresh a row of the second set of memory banks associated with the row address stored in the flip-flop via the address path when the plurality of memory banks is unsynchronized.
8. The system of claim 7 , wherein the plurality of memory banks is synchronized after the command address input circuit refreshes the row of the second set of memory banks associated with the row address stored in the flip-flop.
9. The system of claim 1 , wherein the flip-flop is configured to store the row address when the plurality of memory banks is synchronized.
10. The system of claim 1 , comprising a plurality of bank control blocks coupled to the plurality of memory banks, wherein the plurality of bank control blocks are configured to internally increment the row address upon receiving the row address via the address path.
11. The system of claim 2 , wherein the plurality of memory banks is synchronized when row addresses of the most recently refreshed row of each memory bank of the plurality of memory banks are the same.
12. The system of claim 1 , comprising a multiplexer configured to output the row address from the counter or the row address from the flip-flop based on a selection signal.
13. The system of claim 12 , wherein the multiplexer is configured to output the row address from the counter when the memory banks are synchronized and the selection signal is associated with refreshing the memory banks or the first set of the memory banks.
14. The system of claim 12 , wherein the multiplexer is configured to output the row address from the flip-flop when the memory banks are unsynchronized and the selection signal is associated with refreshing the memory banks, the first set of the memory banks, or the second set of the memory banks.
15. The system of claim 12 , wherein the multiplexer is configured to output an activate row address of the memory banks to be activated based on the selection signal.
16. The system of claim 15 , wherein the multiplexer is configured to output the activate row address when the selection signal is associated with activating the memory banks.