Systems and methods for frequency mode detection and implementation
View Patent ↗The systems and methods provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device. A state of a chip select signal (CS) is identified. When the CS transitions to low from high, a first portion of a command address is captured in a first clock cycle after the CS transitions. When the command acquisition mode is in a first mode, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle. Otherwise, when the command acquisition mode is in a second mode, the second portion of the command address is captured in a third clock cycle immediately following the second clock signal. An internal command is fired, using the first portion of the command address and the second portion of the command address.
1. A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device;
identify a state of a chip select signal (CS);
when the CS transitions to low from high:
capture a first portion of a command address in a first clock cycle after the CS transitions;
when the command acquisition mode is in a first mode, capture a second portion of the command address in a second clock cycle immediately after the first clock cycle;
otherwise, when the command acquisition mode is in a second mode, capture the second portion of the command address in a third clock cycle immediately following the second clock signal; and
fire an internal command, using the first portion of the command address and the second portion of the command address.
2. The machine-readable medium of claim 1 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
when the command acquisition mode is in the second mode maintain a toggle indicating when a cycle is a decode cycle.
3. The machine-readable medium of claim 2 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
when the toggle indicates that a cycle immediately previous to the current cycle is a decode cycle, skip command address acquisition during the current cycle.
4. The machine-readable medium of claim 2 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
when the toggle indicates that a cycle immediately previous to the current cycle is not a decode cycle, perform command address acquisition during the current cycle.
5. The machine-readable medium of claim 2 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
when the CS is low, maintain the toggle by alternating the toggle between a high state and a low state for alternating cycles.
6. The machine-readable medium of claim 1 , wherein the CS is low during the first clock cycle and the second clock cycle.
7. The machine-readable medium of claim 1 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
determine whether a two-cycle command decode indicator is set.
8. The machine-readable medium of claim 7 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
when the two-cycle command decode indicator is set, disable decoding in a current cycle.
9. The machine-readable medium of claim 8 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
when the two-cycle command decode indicator is not set, determine whether a current cycle is a decode cycle.
10. The machine-readable medium of claim 9 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
when the current cycle is a decode cycle, set the two-cycle command decode for a mode-dependent width.
11. The machine-readable medium of claim 10 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
wherein the mode-dependent width comprises one clock cycle when the command acquisition mode is in the first mode.
12. The machine-readable medium of claim 10 , comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
wherein the mode-dependent width comprises two clock cycles when the command acquisition mode is in the second mode.
13. A command interface of a memory device, comprising circuitry, configured to:
identifies a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device;
identifies a state of a chip select signal (CS);
when the CS transitions to low from high:
captures a first portion of a command address in a first clock cycle after the CS transitions;
when the command acquisition mode is in a first mode, captures a second portion of the command address in a second clock cycle immediately after the first clock cycle;
otherwise, when the command acquisition mode is in a second mode, captures the second portion of the command address in a third clock cycle immediately following the second clock signal; and
fires an internal command, using the first portion of the command address and the second portion of the command address.
14. The command interface of claim 13 , comprising circuitry, configured to:
maintains a toggle indicating when a cycle is a decode cycle.
15. The command interface of claim 14 , comprising circuitry, configured to:
determines, via the toggle, that a cycle previous to the current cycle is a decode cycle; and
based upon the cycle immediately previous to the current cycle being a decode cycle, skips command address acquisition during the current cycle.
16. The command interface of claim 14 , comprising circuitry, configured to:
determines, via the toggle, that a cycle immediately previous to the current cycle is not a decode cycle; and
based upon the cycle immediately previous to the current cycle not being a decode cycle, performs command address acquisition during the current cycle.
17. The command interface of claim 14 , comprising circuitry, configured to:
determines whether a two-cycle command decode indicator is set.
18. The command interface of claim 17 , comprising circuitry, configured to:
when the two-cycle command decode indicator is set, disables decoding in a current cycle; and
otherwise, when the two-cycle command decode indicator is not set:
determines whether a current cycle is a decode cycle; and
when the current cycle is a two-cycle command decode cycle, sets the two-cycle command decode for a mode-dependent width;
wherein the mode-dependent width comprises one clock cycle when the command acquisition mode is in the first mode; and
wherein the mode-dependent width comprises two clock cycles when the command acquisition mode is in the second mode.
19. A method, comprising:
identifying a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device;
identifying a state of a chip select signal (CS);
when the CS transitions to low from high:
capturing a first portion of a command address in a first clock cycle after the CS transitions;
when the command acquisition mode is in a first mode, capturing a second portion of the command address in a second clock cycle immediately after the first clock cycle;
otherwise, when the command acquisition mode is in a second mode, capturing the second portion of the command address in a third clock cycle immediately following the second clock signal; and
firing an internal command, using the first portion of the command address and the second portion of the command address.
20. The method of claim 19 , comprising:
determining whether a two-cycle command decode indicator is set;
determining the first clock cycle, using the two-cycle command decode indicator.