IP Library Granted Patent US 10,096,380
Granted Patent B1
US 10,096,380 · App. 15/692,962 · Granted Oct 9, 2018

Erase page check

Inventors: Ting Luo (Santa Clara, CA); Scott Anthony Stoller (Boise, ID); Preston Thomson (Boise, ID); Devin Batutis (San Jose, CA); Harish Singidi (Fremont, CA); Kulachet Tanpairoj (Santa Clara, CA)
Assignee: Micron Technology, Inc.
G11C29/38G06F11/073G06F11/079G06F11/0751G06F11/0793G11C29/44
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Quick Facts
Patent No.
US 10,096,380
App. No.
15/692,962
Granted
Oct 9, 2018
Kind
B1
Abstract

Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

Claims (43)

1. A method performed by a controller of a memory device, the method comprising:

determining that an asynchronous power loss occurred; and

responsive to determining that the asynchronous power loss occurred:

identifying a memory cell of the memory device to test for an incomplete programming operation, the memory cell configured as a multi-level cell;

shifting a read voltage of a first page of the memory cell of a predetermined magnitude toward a zero voltage, the first page having a lowest read voltage of a plurality of pages of the memory cell;

reading a value in the first page of the memory cell using the shifted read voltage;

determining that the memory cell was incompletely programmed based upon the value; and

in response to determining that the memory cell was incompletely programmed, mark the memory cell for erasure.

2. The method of claim 1 , wherein the first page is an extra page.

3. The method of claim 1 , wherein the first page is an upper page.

4. The method of claim 1 , wherein the asynchronous power loss is an unexpected power loss and wherein determining that the asynchronous power loss occurred comprises determining that a shut-down indication is not present on a power up.

5. The method of claim 1 , wherein reading the value in the first page is a user-mode read operation.

6. The method of claim 1 , wherein the first page is not a lower page.

7. The method of claim 1 , wherein identifying the memory cell of the memory device to test for the incomplete programming operation comprises finding a last fully written memory cell.

8. A memory device comprising:

a controller, configured to perform operations comprising:

determining that an asynchronous power loss occurred; and

responsive to determining that the asynchronous power loss occurred:

identifying a memory cell of the memory device to test for an incomplete programming operation, the memory cell configured as a multi-level cell;

shifting a read voltage of a first page of the memory cell of a predetermined magnitude toward a zero voltage, the first page having a lowest read voltage of a plurality of pages of the memory cell;

reading a value in the first page of the memory cell using the shifted read voltage;

determining that the memory cell was incompletely programmed based upon the value; and

in response to determining that the memory cell was incompletely programmed; mark the memory cell for erasure.

9. The memory device of claim 8 , wherein the first page is an extra page.

10. The memory device of claim 8 , wherein the first page is an upper page.

11. The memory device of claim 8 , wherein the asynchronous power loss is an unexpected power loss and wherein the operations of determining that the asynchronous power loss occurred comprises operations of determining that a shut-down indication is not present on a power up.

12. The memory device of claim 8 , wherein the operations of reading the value in the first page is a user-mode read operation.

13. The memory device of claim 8 , wherein the first page is not a lower page.

14. The memory device of claim 8 , wherein the operations of identifying the memory cell of the memory device to test for the incomplete programming operation comprises operations of finding a last fully written memory cell.

15. A non-transitory machine readable medium comprising instructions, that when executed by a machine, cause the machine to perform operations comprising:

determining that an asynchronous power loss occurred; and

responsive to determining that the asynchronous power loss occurred:

identifying a memory cell of a memory device to test for an incomplete programming operation, the memory cell configured as a multi-level cell;

shifting a read voltage of a first page of the memory cell of a predetermined magnitude toward a zero voltage, the first page having a lowest read voltage of a plurality of pages of the memory cell;

reading a value in the first page of the memory cell using the shifted read voltage;

determining that the memory cell was incompletely programmed based upon the value; and

in response to determining that the memory cell was incompletely programmed, mark the memory cell for erasure.

16. The non-transitory machine readable medium of claim 15 , wherein the first page is an extra page.

17. The non-transitory machine readable medium of claim 15 , wherein the first page is an upper page.

18. The non-transitory machine readable medium of claim 15 , wherein the asynchronous power loss is an unexpected power loss and wherein the operations of determining that the asynchronous power loss occurred comprises operations of determining that a shut-down indication is not present on a power up.

19. The non-transitory machine readable medium of claim 15 , wherein the operations of reading the value in the first page is a user-mode read operation.

20. The non-transitory machine readable medium of claim 15 , wherein the first page is not a lower page.

21. The non-transitory machine readable medium of claim 15 , wherein the operations of identifying the memory cell of the memory device to test for the incomplete programming operation comprises operations of finding a last fully written memo cell.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2018
From: LUO, TING; STOLLER, SCOTT ANTHONY; THOMSON, PRESTON; BATUTIS, DEVIN; SINGIDI, HARISH REDDY; TANPAIROJ, KULACHET
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046706/0510 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →