Apparatuses and methods for storing a data value in a sensing circuitry element

1. A method, comprising:

moving a first data value from a first storage location of a compute component of a sensing circuitry element to a second storage location of the compute component,

wherein moving the first data value includes applying a charge sharing operation between the first storage location and the second storage location.

2. The method of claim 1 , further comprising controlling logic circuitry of the sensing circuitry element to perform a logical operation on the first data value and a second data value.

3. The method of claim 1 , wherein the charge sharing operation comprises shorting a node of the first storage location to a node of the second storage location.

4. The method of claim 1 , wherein the charge sharing operation comprises gating nodes associated with the logic circuitry to isolate logic circuitry during the charge sharing operation.

5. The method of claim 1 , wherein the charge sharing operation comprises:

applying a first voltage to the first storage location;

applying a second voltage to the second storage location; and

stopping the application of the first voltage to the first storage location in response to the second voltage being applied to the second storage location.

6. The method of claim 1 , further comprising storing, in the first storage location, a third data value resulting from a logical operation performed using the first data value and a second data value.

7. The method of claim 1 , wherein applying the charge sharing operation comprises stopping an application of a voltage to the first storage location and the second storage location to share a charge associated with the first storage location and the second storage location.

8. An apparatus, comprising:

a sensing circuitry element including a sense amplifier and a compute component, the compute component comprising a first storage location and a second storage location; and

a controller coupled to the sensing circuitry element and configured to:

move a first data value from the first storage location of the compute component to the second storage location of the compute component by applying a charge sharing operation between the first storage location and the second storage location.

9. The apparatus of claim 8 , wherein the controller is further configured to cause a node of the first storage location to be shorted to a node of the second storage location as part of the charge sharing operation.

10. The apparatus of claim 8 , wherein:

the sensing circuitry element further comprises logic, and

the controller is configured to cause the logic circuitry to perform a logical operation on the first data value and a second data value.

11. The apparatus of claim 10 , wherein the controller is further configured to cause a third data value resulting from performance of the logical operation to be stored in the first storage location.

12. The apparatus of claim 8 , further comprising a plurality of transistors coupled to the compute component, wherein the controller is configured to assert a precharge signal to gates transistors among the plurality of transistors as part of application of the charge sharing operation.

13. An apparatus, comprising:

a sensing circuitry element, including:

a sense amplifier coupled to logic circuitry;

a first storage location coupled to the logic circuitry; and

a second storage location coupled to the first storage location; and

a controller coupled to the sensing circuitry element, wherein the controller is configured to:

disable, during a clock cycle, a power associated with the first storage location; and

disable, during the clock cycle, a power associated with the second storage location such that a charge between the first storage location and the second storage location is shared.

14. The apparatus of claim 13 , wherein the controller is further configured to cause a logical operation to be performed on a first data value stored in the sense amplifier and a second data value stored in the second storage location.

15. The apparatus of claim 14 , wherein the controller is further configured to cause a result of the logical operation to be stored in the first storage location.

16. The apparatus of claim 14 , wherein the controller is configured to cause the logical operation to be performed without transferring the first data value or the second data value via an input/output (I/O) line.

17. The apparatus of claim 13 , wherein the sensing circuitry element is configured to act as a single-bit processing element capable of performing a logical operation in parallel with other sensing circuitry elements.

18. The apparatus of claim 13 , further comprising:

a first transistor coupled to the first storage location;

a second transistor coupled to the second storage location, wherein a gate of the first transistor and a gate of the second transistor are coupled to a precharge signal line.

19. The apparatus of claim 13 , wherein the controller is configured to control coupling a node of the first storage location to a node of the second location such that the node of the first storage location is shorted to the node of the second location such that the charge between the first storage location and the second storage location is shared.

20. The apparatus of claim 13 , wherein the controller is configured to cause a data value stored in the first storage location to be shifted to the second storage location.