IP Library › Granted Patent US 10,418,979
Granted Patent B2
US 10,418,979 · App. 15/693,343 · Granted Sep 17, 2019

Jitter-free ring oscillator

Inventor: Teh-Shang Lu (Sunnyvale, CA)
Assignee: Core Chip Technology (Nanjing) Co., Ltd.
H03K3/0322H03K3/013H03K3/0315
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Quick Facts
Patent No.
US 10,418,979
App. No.
15/693,343
Granted
Sep 17, 2019
Kind
B2
Abstract

A ring oscillator includes: (i) one or more current sources each connected to a supply voltage source; and (ii) oscillation elements connected in series in a ring configuration each element including: (a) first and second input terminals; (b) first and second output terminals; (c) first and second inverters receiving input signals from the first and second input terminals, respectively, and providing output signals on the first and second output terminals, respectively; and (d) third and fourth inverters, each having an input terminal and an output terminal, wherein the input terminals of the third and fourth inverters are coupled to the first and second output terminals of the oscillator element, respectively, wherein the output terminals of third and fourth inverters are coupled to the second and first output terminals of the oscillator element, respectively, and wherein each of first, second, third and fourth inverters are coupled to the supply voltage source through the current sources.

Claims (10)

1. A ring oscillator, which comprises:

a plurality of current sources each connected to a supply voltage source; and

a plurality of oscillation elements connected in series in a ring configuration, wherein successive oscillator elements in the series draw currents from different current sources and wherein at least two of the oscillator elements draw current from one of the current sources, each oscillator element comprising:

first and second input terminals;

first and second output terminals;

first and second inverters receiving input signals from the first and second input terminals, respectively, and providing output signals on the first and second output terminals, respectively; and

third and fourth inverters, each having an input terminal and an output terminal, wherein the input terminals of the third and fourth inverters are coupled to the first and second output terminals of the oscillator element, respectively, wherein the output terminals of third and fourth inverters are coupled to the second and first output terminals of the oscillator element, respectively, and wherein the current sources providing currents to the oscillator element couple the first, the second, the third and the fourth inverters to the supply voltage source.

2. The ring oscillator of claim 1 , wherein the first and second inverters are each larger than either one of the third and fourth inverters.

3. The ring oscillator of claim 1 , wherein the successive oscillator elements provide output signals on their respective first output terminals that bear a predetermined phase relationship relative to each other.

4. The ring oscillator of claim 3 , wherein the predetermined phase relationship is one or more times of ±90°.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2018
From: AUCMOS TECHNOLOGIES USA, INC.
To: CORE CHIP TECHNOLOGY (NANJING) CO., LTD.
Reel/Frame 046821/0597 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2018
From: LU, TEH-SHANG
To: AUCMOS TECHNOLOGIES USA, INC.
Reel/Frame 046553/0492 →
Continuity (1)
Related Publication 20190068174A1 · Feb 28, 2019