IP Library Granted Patent US 10,176,776
Granted Patent B2
US 10,176,776 · App. 15/693,916 · Granted Jan 8, 2019

Display device and driving circuit

Inventors: Tetsuya Kawamura (Hyogo, JP); Hironori Yasukawa (Hyogo, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
G09G3/3648G02F1/1345G09G3/3611G02F1/136286G09G2300/0426G09G2300/0465G09G2310/0264G09G2310/0281G09G2310/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,176,776
App. No.
15/693,916
Granted
Jan 8, 2019
Kind
B2
Abstract

Provided is a display device, including: a driving circuit including a first output terminal group including at least one gate signal output terminal, and a second output terminal group including at least one source signal output terminal; and a plurality of gate lead-out lines configured to transmit a gate signal to a plurality of gate lines, in which each of the plurality of gate lines is electrically connected to at least one of the gate lead-out lines, and the first output terminal group is arranged between two adjacent second output terminal groups.

Claims (14)

1. A driving circuit, which is configured to respectively output a gate signal and a source signal to a gate line and a source line formed in a display panel, the driving circuit comprising:

a first output terminal group comprising at least one gate signal output terminal configured to output the gate signal; and

a second output terminal group comprising at least one source signal output terminal configured to output the source signal,

wherein the first output terminal group is arranged between two adjacent second output terminal groups,

the first output terminal group and the two adjacent second output terminal groups are arranged in a first direction,

the driving circuit further comprising a plurality of bumps, the plurality of bumps including a first bump and a second bump,

the first bump is configured to output the gate signal and is electrically connected with a gate bundled line,

the second bump is configured to output the source signal and is electrically connected with a source lead-out line via a metal wiring, and

the gate bundled line and the metal wiring are formed in a same layer.

2. The driving circuit according to claim 1 ,

wherein the first output terminal group comprises a left first output terminal group, a middle first output terminal group and a right first output terminal group, the left first output terminal group, the middle first output terminal group and the right first output terminal group being arranged in the first direction,

wherein a number of the source signal output terminals arranged between the left first output terminal group and the middle first output terminal group is equal to a number of the source signal output terminals arranged between the middle first output terminal group and the right first output terminal group.

3. The driving circuit according to claim 2 ,

wherein the number of the source signal output terminals arranged between the left first output terminal group and the middle first output terminal group is more than the number of gate signal outputs included in the middle first output terminal group.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
Priority Claims (1)
JP 2014-199437 · Sep 29, 2014 · national
Continuity (2)
Continuation 14867417 · Sep 28, 2015
Related Publication 20170365227A1 · Dec 21, 2017