Non-volatile semiconductor memory device including clamp circuit with control transistor and amplifier circuit
A non-volatile semiconductor memory device includes a current source providing a reference current to a first node and a clamp circuit. The clamp circuit includes a transistor having a current path between the first node and a second node, and an amplifier circuit having a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the transistor. The amplifier circuit is configured to output a differentially amplified signal from the output port. A memory cell is connected between a bit line and a word line and includes a variable resistance element. The bit line can be connected to the second node. A sense amplifier is connected to the first node to detect data stored in the memory cell.
1. A non-volatile semiconductor memory device, comprising:
a current source providing a reference current to a first node;
a clamp circuit including:
a control transistor having a current path with a first end connected to the first node and a second end connected to a second node, and
an amplifier circuit with a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the control transistor, the amplifier circuit being configured to output a differentially amplified signal from the output port;
a memory cell connected between a bit line and a word line and including a variable resistance element, the bit line being connectable to the second node;
a sense amplifier connected to the first node and configured to detect a data value stored in the memory cell according to a resistance level of the variable resistance element;
a first switch between the first node and a first reference voltage source, the first switch being configured to connect the first node to the first reference voltage source when a first control signal provided thereto is in an enable state; and
a second switch between the second node and the bit line, the second switch being configured to connect the second node to the bit line when a second control signal provided thereto is in an enable state.
2. The non-volatile semiconductor memory device according to claim 1 , wherein
the sense amplifier includes a capacitor, an inverter, and a third switch, and
the capacitor is connected between the first node and an input side of the inverter,
a first end of the third switch is connected a node between the capacitor and the input side of the inverter and the capacitor,
a second end of the third switch the output side of the inverter, and
when the third switch is closed, the third switch connects the node between the capacitor and the input side of the inverter to the output side of the inverter to feed an output signal of the inverter back to the input side of the inverter.
3. The non-volatile semiconductor memory device according to claim 1 , wherein the variable resistance element stores a plurality of data items as multilevel data items at resistance value distributions that are different from each other.
4. The non-volatile semiconductor memory device according to claim 3 , further comprising:
a determination circuit configured to receive an output signal from the sense amplifier and change the cell reference voltage according to the output signal from the sense amplifier; and
a digital-to-analog converter that outputs a voltage for changing the cell reference voltage according to the determination circuit.
5. The non-volatile semiconductor memory device according to claim 1 , wherein the memory cell is one of a resistive random access memory (ReRAM)-type, a phase-change random access memory (PCRAM)-type, or a magneto-resistive random access memory (MRAM)-type.
6. The non-volatile semiconductor memory device according to claim 1 , wherein the current source includes a current mirror circuit.
7. The non-volatile semiconductor memory device according to claim 6 , wherein the current mirror circuit comprises two p-channel metal-oxide-semiconductor transistors.
8. The non-volatile semiconductor memory device according to claim 7 , wherein a ratio of gate width to gate length is the same for the two p-channel metal-oxide semiconductor transistors.
9. A non-volatile semiconductor memory device, comprising:
a memory cell array including a memory cell connected between a bit line and a word line, the memory cell including variable resistance element for storing data;
a write-read circuit connected to the memory cell array for writing and reading data according to commands from an external host;
an address decoder for controlling selection of the bit line and selection of the word line according to the commands from the external host;
a controller configured to control the write-read circuit and the address decoder according to the commands from the external host, wherein
the write-read circuit includes:
a current source providing a reference current to a first node;
a clamp circuit including:
a control transistor having a current path with a first end connected to the first node and a second end connected to a second node to which the bit line can be connected, and
an amplifier circuit with a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the control transistor, the amplifier circuit being configured to output a differentially amplified signal from the output port; and
a sense amplifier connected to the first node and configured to detect a data value stored in the memory cell according to a resistance level of the variable resistance element;
a first switch between the first node and a first reference voltage source, the first switch being configured to connect the first node to the first reference voltage source when a first control signal provided thereto from the controller is in an enable state; and
a second switch between the second node and the bit line, the second switch being configured to connect the second node to the bit line when a second control signal provided thereto from the controller is in an enable state.
10. The non-volatile semiconductor memory device according to claim 9 , wherein
the sense amplifier includes a capacitor, an inverter, and a third switch, and
the capacitor is connected between the first node and an input side of the inverter,
a first end of the third switch is connected a node between the capacitor and the input side of the inverter and the capacitor,
a second end of the third switch is connected to the output side of the inverter, and
when the third switch is closed, the third switch connects the node between the capacitor and the input side of the inverter to the output side of the inverter to feed an output signal of the inverter back to the input side of the inverter.
11. The non-volatile semiconductor memory device according to claim 9 , wherein the variable resistance element stores a plurality of data items as multilevel data items at resistance value distributions that are different from each other.
12. The non-volatile semiconductor memory device according to claim 11 , further comprising:
a determination circuit configured to receive an output signal from the sense amplifier and change the cell reference voltage according to the output signal from the sense amplifier; and
a digital-to-analog converter that outputs a voltage for changing the cell reference voltage according to the determination circuit.
13. The non-volatile semiconductor memory device according to claim 9 , wherein the memory cell is one of a resistive random access memory (ReRAM)-type, a phase-change random access memory (PCRAM)-type, or a magneto-resistive random access memory (MRAM)-type.
14. The non-volatile semiconductor memory device according to claim 9 , wherein the current source includes a current mirror circuit.
15. A non-volatile semiconductor memory device, comprising:
a current source including a current mirror circuit and providing a reference current to a first node;
a clamp circuit including:
a control transistor having a current path with a first end connected to the first node and a second end connected to a second node, and
an amplifier circuit with a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the control transistor, the amplifier circuit being configured to output a differentially amplified signal from the output port;
a memory cell connected between a bit line and a word line and including a variable resistance element, the bit line being connectable to the second node;
a sense amplifier connected to the first node and configured to detect a data value stored in the memory cell according to a resistance level of the variable resistance element, the sense amplifier including a capacitor and an inverter connected in series and a first switch on a direct path between an input side of the inverter and an output side of the inverter when closed;
a second switch between the first node and a first reference voltage source, the second switch being configured to connect the first node to the first reference voltage source when a first control signal provided thereto is in an enable state; and
a third switch between the second node and the bit line, the third switch being configured to connect the second node to the bit line when a second control signal provided thereto is in an enable state.
16. The non-volatile semiconductor memory device according to claim 15 , further comprising:
a determination circuit configured to receive an output signal from the sense amplifier and change the cell reference voltage according to the output signal from the sense amplifier; and
a digital-to-analog converter that outputs a voltage for changing the cell reference voltage according to the determination circuit.
17. The non-volatile semiconductor memory device according to claim 15 , wherein the memory cell is one of a resistive random access memory (ReRAM)-type, a phase-change random access memory (PCRAM)-type, or a magneto-resistive random access memory (MRAM)-type.
18. The non-volatile semiconductor memory device according to claim 15 , wherein the variable resistance element stores a plurality of data items as multilevel data items at resistance value distributions that are different from each other.
19. A non-volatile semiconductor memory device, comprising:
a current source providing a reference current to a first node;
a clamp circuit including:
a control transistor having a current path with a first end connected to the first node and a second end connected to a second node, and
an amplifier circuit with a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the control transistor, the amplifier circuit being configured to output a differentially amplified signal from the output port;
a memory cell connected between a bit line and a word line and including a variable resistance element, the bit line being connectable to the second node;
a sense amplifier connected to the first node and configured to detect a data value stored in the memory cell according to a resistance level of the variable resistance element;
a determination circuit configured to receive an output signal from the sense amplifier and change the cell reference voltage according to the output signal from the sense amplifier; and
a digital-to-analog converter that outputs a voltage for changing the cell reference voltage according to the determination circuit, wherein
the variable resistance element stores a plurality of data items as multilevel data items at resistance value distributions that are different from each other.
20. The non-volatile semiconductor memory device according to claim 19 , wherein the memory cell is one of a resistive random access memory (ReRAM)-type, a phase-change random access memory (PCRAM)-type, or a magneto-resistive random access memory (MRAM)-type.