SEMICONDUCTOR CHIP, SEMICONDUCTOR APPARATUS, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER DICING METHOD

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Quick Facts

Patent No.: US None
App. No.: 15/695,357

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Abstract

Provided are a semiconductor chip, a semiconductor apparatus, a semiconductor wafer, and a semiconductor wafer dicing method in which chipping is prevented while securing an effective region of the semiconductor chip to have a sufficient area. Each semiconductor chip region which becomes a semiconductor chip has a rectangular shape, and includes non-effective regions in which no circuit device is placed. The non-effective regions are provided only at two corner portions located at two ends of an arbitrary side of the rectangular shape. The semiconductor wafer has a plurality of semiconductor chip regions arranged so that all non-effective regions face the traveling direction of a dicing blade in a second dicing step.

Claims (33)

1 . A semiconductor chip, comprising a principal surface having a shape of a rectangle having four sides,

the principal surface comprising:

non-effective regions in which no circuit device is placed, the non-effective regions being provided only at two corner portions that are located at two ends of one arbitrary side out of the four sides; and

an effective region in which a circuit device is placed, the effective region being provided in a remaining region other than the non-effective regions.

2 . A semiconductor chip according to claim 1 , wherein each of the non-effective regions has a shape of a right triangle that has a longer side about the right angle along a direction perpendicular to the one arbitrary side, and has a right-angled portion matching with one of the two corner portions.

3 . A semiconductor chip according to claim 1 , wherein each of the non-effective regions has a shape smaller in area than a right triangle that has a right-angled portion formed by a first straight line portion and a second straight line portion which is longer than the first straight line portion, and that is formed from a straight line connecting an end portion of the first straight line portion and an end portion of the second straight line portion, the first straight line portion, and the second straight line portion, the right-angled portion matching with one of the two corner portions, the first straight line portion being located along the one arbitrary side, the end portion of the first straight line portion being opposite from the right-angled portion, the end portion of the second straight line portion being opposite from the right-angled portion.

4 . A semiconductor chip according to claim 1 ;

wherein each of the non-effective regions has a right-angled portion formed from a first straight line portion and a second straight line portion which is longer than the first straight line portion, the right-angled portion matching with one of the two corner portions, the first straight line portion being located along the one arbitrary side, and

wherein each of the non-effective regions has a shape smaller in area than a right triangle constructed by the first straight line portion, the second straight line portion, and a straight line connecting an end portion of the first straight line portion opposite to the right-angled portion and an end portion of the second straight line portion opposite to the right-angled portion.

5 . A semiconductor chip according to claim 1 , further comprising a crack stopper region provided along each border portion between the non-effective regions and the effective region.

6 . A semiconductor chip according to claim 5 , wherein the crack stopper region comprises one of a wall, a groove, and a step, which are formed in a surface of the semiconductor chip.

7 . A semiconductor apparatus, comprising the semiconductor chip of claim 1 , the semiconductor chip being sealed with resin.

8 . A semiconductor wafer, comprising a plurality of semiconductor chip regions and a plurality of dicing lines which are alternated and aligned in a first direction and a second direction which is perpendicular to the first direction,

each of the plurality of semiconductor chip regions having a rectangular shape and comprising non-effective regions and an effective region, the non-effective regions being provided only at two corner portions that are located at two ends of one side along the first direction, the non-effective regions having no circuit device, the effective region being provided in a remaining region other than the non-effective regions, the effective region having a circuit device,

the one side of each of the plurality of semiconductor chip regions being on the same straight line as the one side of each of other semiconductor chip regions that are aligned in the same row as the each of the plurality of semiconductor chip regions in the first direction, and

the non-effective regions being equally spaced from one another in the second direction.

9 . A semiconductor wafer according to claim 8 , wherein each of the non-effective regions has a shape of a right triangle that has a longer side about the right angle along the second direction, and has a right-angled portion matching with one of the two corner portions.

10 . A semiconductor chip according to claim 8 ;

wherein each of the non-effective regions has a right-angled portion formed from a first straight line portion in parallel to the first direction and a second straight line portion in parallel to the second direction, the second straight line portion being longer than the first straight line portion, the right-angled portion matching with one of the two corner portions, and

11 . A semiconductor wafer according to claim 8 , further comprising a crack stopper region provided along each border portion between the non-effective regions and the effective region.

12 . A semiconductor wafer according to claim 11 , wherein the crack stopper region comprises one of a wall, a groove, and a step which are formed in a surface of the semiconductor chip region.

13 . A semiconductor wafer dicing method, comprising:

a step of preparing a semiconductor wafer on which a plurality of semiconductor chip regions and a plurality of dicing lines are alternated and aligned longitudinally and laterally;

a first dicing step of dicing the semiconductor wafer into strips along dicing lines that run in a first direction out of the plurality of dicing lines, by using a dicing blade; and

a second dicing step of dicing the semiconductor wafer into a plurality of individual semiconductor chips along dicing lines that run in a second direction perpendicular to the first direction out of the plurality of dicing lines, by using the dicing blade,

wherein each of the plurality of semiconductor chip regions has a rectangular shape and comprises non-effective regions and an effective region, the non-effective regions being provided only at two corner portions that face a traveling direction of the dicing blade in the second dicing step, the non-effective regions comprising no circuit device, the effective region being provided in a remaining region other than the non-effective regions, the effective region comprising a circuit device.

14 . A semiconductor wafer dicing method according to claim 13 , wherein each of the non-effective regions has a shape of a right triangle that has a longer side about the right angle along the second direction and has a right-angled portion matching with one of the two corner portions.

15 . A semiconductor chip according to claim 13 ;

16 . A semiconductor wafer dicing method according to claim 13 , wherein each of the plurality of semiconductor chip regions further comprises a crack stopper region provided along each border portion between the non-effective regions and the effective region.

17 . A semiconductor wafer dicing method according to claim 16 , wherein the crack stopper region comprises one of a wall, a groove, and a step, which are formed in a surface of the semiconductor chip region.

Assignments (2)

CHANGE OF NAME Recorded Mar 12, 2018

From: SII SEMICONDUCTOR CORPORATION

To: ABLIC INC.

Reel/Frame 045567/0927 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2017

From: UTSUNOMIYA, HIROYUKI

To: SII SEMICONDUCTOR CORPORATION

Reel/Frame 043488/0496 →