IP Library Granted Patent US 10,324,860
Granted Patent B2
US 10,324,860 · App. 15/695,683 · Granted Jun 18, 2019

Memory heaps in a memory model for a unified computing system

Inventors: Anthony Asaro (Markham, CA); Kevin Normoyle (Los Gatos, CA); Mark Hummel (Franklin, MA)
Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC
G06F12/1036G06F12/0284G06F12/0646G06F12/08G06F12/109G06F12/10G06F2212/1012G06F2212/152G06F2212/656G06F2212/657
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Quick Facts
Patent No.
US 10,324,860
App. No.
15/695,683
Granted
Jun 18, 2019
Kind
B2
Abstract

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Claims (27)

1. A method for allocating memory in a processing system having at least two processors, the method comprising:

receiving a memory access request for a shared memory address from one processor of the at least two processors; and

mapping the shared memory address to at least two virtual memory pools of a plurality of virtual memory pools, wherein each virtual memory pool is associated with at least one memory resource; and

providing a mapping result to the one processor of the at least two processors.

2. The method of claim 1 , wherein at least one virtual memory pool is associated with at least one physical memory resource.

3. The method of claim 2 , wherein the at least one physical memory resource is at least two physical memory resources.

4. The method of claim 1 , wherein at least one of the virtual memory pools is not accessible by one of at least two processors which share the shared memory address, and at least one of the virtual memory pools is accessible by all of the at least two processors.

5. The method of claim 4 , wherein at least one virtual memory pool is only accessible by a single group of first processor threads.

6. The method of claim 5 , wherein at least one virtual memory pool is only accessible by a single application.

7. The method of claim 1 , wherein at least one virtual memory pool is only accessible by a specific one of at least two processors which share the shared memory address.

8. The method of claim 1 , wherein at least one virtual memory pool is mapped to a physical memory upon initiation of an associated processor thread.

9. The method of claim 1 , wherein at least one virtual memory pool is accessible by all of at least two processors which share the shared memory address and the at least one virtual memory pool is mapped to a physical memory resource associated with one processor of the at least two processors using a page table associated with the one processor.

10. The method of claim 1 , wherein at least one virtual memory pool is only accessible by a specific type of processor.

11. The method of claim 1 , wherein a type of processor imparts different attributes on a mapped memory.

12. A system having at least two processors, comprising:

a plurality of memory resources;

a plurality of virtual memory pools, each being associated with at least one memory resource;

a mapper configured to receive a memory access request for a shared memory address from one processor of the at least two processors; and

the mapper further configured to map the shared memory address to at least two virtual memory pools of the plurality of virtual memory pools and to provide a mapping result to the one processor of the at least two processors, wherein each virtual memory pool is associated with at least one of the plurality of memory resources.

13. The system of claim 12 , wherein different attributes are applied to a mapped virtual memory pool depending upon origination of the access request.

14. The system of claim 12 , wherein at least one of the plurality of virtual memory pools is mapped to a first processor memory resource using a page table and is accessible by the at least two processors.

15. The system of claim 12 , wherein at least one of the plurality of virtual memory pools is not accessible by a first processor, at least another virtual memory pool is not accessible by a second processor, and at least another virtual memory pool is accessible by the first processor and the second processor.

16. The system of claim 12 , wherein at least one of the plurality of virtual memory pools is accessible by a first processor, is not accessible by a second processor, and is an allocated memory space in a memory resource associated with the first processor.

17. The system of claim 12 , wherein at least one virtual memory pool is only accessible by a specific one of the at least two processors.

18. The system of claim 12 , wherein at least one virtual memory pool is only accessible by a specific type of processor.

19. The system of claim 12 , wherein a type of processor imparts different attributes on a mapped memory.

20. The system of claim 12 , wherein at least one virtual memory pool is associated with at least one physical memory resource.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2024
From: ADVANCED MICRO DEVICES, INC.
To: ONESTA IP, LLC
Reel/Frame 069381/0951 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2024
From: ATI TECHNOLOGIES ULC
To: ONESTA IP, LLC
Reel/Frame 069379/0556 →
Continuity (5)
Continuation 15254466 · Sep 1, 2016
Continuation 14833850 · Aug 24, 2015
Continuation 13724879 · Dec 21, 2012
Provisional Application 61617405 · Mar 29, 2012
Related Publication 20180011798A1 · Jan 11, 2018