Computer system and a computer device
View Patent ↗A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.
1. A computer system comprising:
a bus;
a hub portion coupled to the bus, the hub portion including an input/output controller configured to communicate with a plurality of periphery devices; and
a plurality of units, each unit being in communication with the bus and two or more of the units being coupled in series, each unit is configurable to operate as at least one of a node, a network controller, a disk controller, and a portion of a memory controller, wherein the node, the network controller, the disk controller, and the portion of the memory controller include dedicated memory and an embedded application kernel to pre-fetch data, wherein the memory controller utilizes two or more of the units in the plurality of units coupled in series for staging prefetching operations;
wherein each unit in the plurality of units is capable of at least one of hosting an operating system different from another operating system being hosted by another of the units, and, hosting an operating system being used by at least another of the units, each unit having a dedicated physical resource for the operating system hosting, each unit is capable of communicating with the hub portion using the bus, and, each unit is capable of communicating with each of the other units included in the plurality of units.
2. The computer system of claim 1 , wherein the plurality of units is included in a field programmable gate array.
3. The computer system of claim 1 , comprising at least one solid state memory drive.
4. The computer system of claim 1 , wherein one of the units hosts a first operating system and another of the units hosts a second operating system, different from the first operating system.
5. The computer system of claim 1 , wherein one of the units and another of the units host one operating system.
6. The computer system of claim 1 , wherein the memory controller is configured to connect to a storage device external to the computer system.
7. A computer system comprising:
a bus;
a hub portion coupled to the bus, the hub portion including an input/output controller configured to communicate with a plurality of periphery devices; and
a plurality of units, each unit being in communication with the bus and two or more of the units being coupled in parallel, each unit is configurable to operate as at least one of a node, a network controller, a disk controller, and a portion of a memory controller, wherein the node, the network controller, the disk controller, and the portion of the memory controller include dedicated memory and an embedded application kernel to pre-fetch data, wherein the memory controller utilizes two or more of the units in the plurality of units coupled in parallel for staging prefetching operations;
wherein each unit in the plurality of units is capable of at least one of hosting an operating system different from another operating system being hosted by another of the units, and, hosting an operating system being used by at least another of the units, each unit having a dedicated physical resource for the operating system hosting, each unit is capable of communicating with the hub portion using the bus, and, each unit is capable of communicating with each of the other units included in the plurality of units.
8. The computer system of claim 7 , wherein the plurality of units is included in a field programmable gate array.
9. The computer system of claim 7 , comprising at least one solid state memory drive.
10. The computer system of claim 7 , wherein one of the units hosts a first operating system and another of the units hosts a second operating system, different from the first operating system.
11. The computer system of claim 7 , wherein one of the units and another of the units host one operating system.
12. The computer system of claim 7 , wherein the memory controller is configured to connect to a storage device external to the computer system.
13. A computer board comprising:
a bus;
a hub portion coupled to the bus, the hub portion including an input/output controller configured to communicate with a plurality of periphery devices; and
a plurality of units, each unit being in communication with the bus and two or more of the units being coupled in series, each unit is configurable to operate as at least one of a node, a network controller, a disk controller, and a portion of a memory controller, wherein the node, the network controller, the disk controller, and the portion of the memory controller include dedicated memory and an embedded application kernel to pre-fetch data, wherein the memory controller utilizes two or more of the units in the plurality of units coupled in series for staging prefetching operations;
wherein each unit in the plurality of units is capable of at least one of hosting an operating system different from another operating system being hosted by another of the units, and, hosting an operating system being used by at least another of the units, each unit having a dedicated physical resource for the operating system hosting, each unit is capable of communicating with the hub portion using the bus, and, each unit is capable of communicating with each of the other units included in the plurality of units.
14. The computer board of claim 13 , wherein the plurality of units is included in a field programmable gate array.
15. The computer board of claim 13 , comprising at least one solid state memory drive.
16. The computer board of claim 13 , wherein one of the units hosts a first operating system and another of the IC units hosts a second operating system, different from the first operating system.
17. The computer board of claim 13 , wherein one of the units and another of the units host one operating system.
18. The computer board of claim 13 , wherein the memory controller is configured to connect to a storage device external to the computer system.
19. A computer board comprising:
a bus;
a hub portion coupled to the bus, the hub portion including an input/output controller configured to communicate with a plurality of periphery devices; and
a plurality of units, each unit being in communication with the bus and two or more of the units being coupled in parallel, each unit is configurable to operate as at least one of a node, a network controller, a disk controller, and a portion of a memory controller, wherein the node, the network controller, the disk controller, and the portion of the memory controller include dedicated memory and an embedded application kernel to pre-fetch data, wherein the memory controller utilizes two or more of the units in the plurality of units coupled in parallel for staging prefetching operations;
wherein each unit in the plurality of units is capable of at least one of hosting an operating system different from another operating system being hosted by another of the units, and, hosting an operating system being used by at least another of the units, each unit having a dedicated physical resource for the operating system hosting, each unit is capable of communicating with the hub portion using the bus, and, each unit is capable of communicating with each of the other units included in the plurality of units.
20. The computer board of claim 19 , wherein the plurality of units is included in a field programmable gate array.
21. The computer board of claim 19 , comprising at least one solid state memory drive.
22. The computer board of claim 19 , wherein one of the units hosts a first operating system and another of the units hosts a second operating system, different from the first operating system.
23. The computer board of claim 19 , wherein one of the units and another of the units host one operating system.
24. The computer board of claim 19 , wherein the memory controller is configured to connect to a storage device external to the computer system.