IP Library Granted Patent US 10,417,092
Granted Patent B2
US 10,417,092 · App. 15/697,566 · Granted Sep 17, 2019

Incremental RAID stripe update parity calculation

Inventors: Timothy Brennan (San Francisco, CA); Marco Sanvido (Belmont, CA); Constantine Sapuntzakis (Mountain View, CA)
Assignee: Pure Storage, Inc.
G06F11/1076G06F3/061G06F3/064G06F3/065G06F3/067G06F3/0619G06F3/0665G06F3/0688
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Quick Facts
Patent No.
US 10,417,092
App. No.
15/697,566
Granted
Sep 17, 2019
Kind
B2
Abstract

Incremental RAID stripe update parity calculation includes receiving a first portion of data of a RAID stripe for writing to a first memory location of a plurality of solid state drives. A first parity value is calculated for the first portion of data of the RAID stripe. A second portion of data of the RAID stripe is received for writing to a second memory location that is different from the first memory location A second parity value is calculated in dependence upon the second portion of the data of the RAID stripe and upon the first parity value Responsive to successfully writing the second portion of data of the RAID stripe, the first parity value is replaced with the second parity value.

Claims (34)

1. A method of incrementally updating RAID (redundant array of independent disks) stripes, the method comprising:

receiving a first portion of data of a RAID stripe for writing to a first memory location of a plurality of solid state drives, wherein the RAID stripe comprises multiple shards;

calculating a first parity value for the first portion of data of the RAID stripe;

receiving a second portion of data of the RAID stripe for writing to a second memory location that is different from the first memory location;

calculating a second parity value in dependence upon the second portion of the data of the RAID stripe and upon the first parity value;

responsive to successfully writing the second portion of data of the RAID stripe, replacing the first parity value with the second parity value, wherein each portion of data of the RAID stripe is written to a memory location within one or more first memory components of a first set of solid state drives; and

responsive to receiving all portions of a shard of the RAID stripe, copying the shard of the RAID stripe from one or more first memory components of the first set of solid state drives to a second memory component of a second set of solid state drives.

2. The method of claim 1 , wherein the second parity value represents parity data for both the first portion of data of the RAID stripe and the second portion of data of the RAID stripe.

3. The method of claim 2 , wherein each portion of data of the RAID stripe defines a distinct portion of a shard of the RAID stripe, and wherein the RAID stripe comprises multiple shards.

4. The method of claim 1 , wherein each portion of data of the RAID stripe is written to a respective memory space that does not overlap with a memory space for another portion of data of the RAID stripe.

5. The method of claim 1 , wherein the one or more first memory components are addressable by a first quantity of bytes.

6. The method of claim 5 , wherein the second memory component of the second set of solid state drives is addressable by a second quantity of bytes that are different from the first quantity of bytes.

7. The method of claim 6 , wherein the one or more first memory components comprise nonvolatile RAM, and wherein the second memory component comprises flash memory.

8. The method of claim 1 , further comprising:

responsive to successfully writing the first portion of data of the RAID stripe: writing a corresponding status indication to a register of a solid state drive implementing a block addressable flash memory.

9. The method of claim 1 , further comprising:

responsive to successfully writing the first portion of data of the RAID stripe: writing a corresponding status indication to a metadata header for a different RAID stripe.

10. An apparatus for incrementally updating RAID (redundant array of independent disks) stripes, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

receiving a first portion of data of a RAID stripe for writing to a first memory location of a plurality of solid state drives, wherein the RAID stripe comprises multiple shards;

calculating a first parity value for the first portion of data of the RAID stripe;

receiving a second portion of data of the RAID stripe for writing to a second memory location that is different from the first memory location;

calculating a second parity value in dependence upon the second portion of the data of the RAID stripe and upon the first parity value;

responsive to successfully writing the second portion of data of the RAID stripe, replacing the first parity value with the second parity value, wherein each portion of data of the RAID stripe is written to a memory location within one or more first memory components of a first set of solid state drives; and

responsive to receiving all portions of a shard of the RAID stripe, copying the shard of the RAID stripe from one or more first memory components of the first set of solid state drives to a second memory component of a second set of solid state drives.

11. The apparatus of claim 10 , wherein the second parity value represents parity data for both the first portion of data of the RAID stripe and the second portion of data of the RAID stripe.

12. The apparatus of claim 11 , wherein each portion of data of the RAID stripe defines a distinct portion of a shard of the RAID stripe, and wherein the RAID stripe comprises multiple shards.

13. The apparatus of claim 10 , wherein each portion of data of the RAID stripe is written to a respective memory space that does not overlap with a memory space for another portion of data of the RAID stripe.

14. The apparatus of claim 10 , wherein the one or more first memory components are addressable by a first quantity of bytes.

15. The apparatus of claim 14 , wherein the second memory component of the second set of solid state drives is addressable by a second quantity of bytes that are different from the first quantity of bytes.

16. The apparatus of claim 15 , wherein the one or more first memory components comprise nonvolatile RAM, and wherein the second memory component comprises flash memory.

17. The apparatus of claim 10 , further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

responsive to successfully writing the first portion of data of the RAID stripe: writing a corresponding status indication to a register of a solid state drive implementing a block addressable flash memory.

18. The apparatus of claim 10 , further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

responsive to successfully writing the first portion of data of the RAID stripe: writing a corresponding status indication to a metadata header for a different RAID stripe.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2017
From: BRENNAN, TIMOTHY; SANVIDO, MARCO; SAPUNTZAKIS, CONSTANTINE
To: PURE STORAGE, INC.
Reel/Frame 043515/0918 →
Continuity (1)
Related Publication 20190073265A1 · Mar 7, 2019
Cited By (9)
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