IP Library › Granted Patent US 12,481,612
Granted Patent B2
US 12,481,612 · App. 17/230,978 · Granted Nov 25, 2025

Mechanism to identify FPGA and SSD pairing in a multi-device environment

Inventors: Oscar P. Pinto (San Jose, CA); Ramdas P. Kachare (Pleasanton, CA)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F13/4022G06F13/1668G06F13/4282G06F2213/0026
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Quick Facts
Patent No.
US 12,481,612
App. No.
17/230,978
Granted
Nov 25, 2025
Kind
B2
Abstract

A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.

Claims (30)

1 . A first device, comprising:

a hardware interface connecting the first device and a second device,

a first storage for a unique first device identifier (ID), the unique first device ID associated with the first device; and

a second storage for a unique second device ID, the unique second device ID associated with the second device,

wherein the first device is configured to receive a query from an operating system about the first device and the second device and to respond to the query from the operating system with the unique first device ID and the unique second device ID.

2 . The first device according to claim 1 , wherein:

the first device includes a storage device, including a third storage for data and a controller to manage writing the data to the third storage and reading the data from the third storage; and

the second device includes one of a Field Programmable Gate Array (FPGA), a Graphics Processing Unit (GPU), a Tensor Processing Unit, and an Erasure Coding Controller.

3 . The first device according to claim 2 , wherein the storage device includes a Solid State Drive (SSD).

4 . The first device according to claim 1 , wherein:

the first device includes one of a Field Programmable Gate Array (FPGA), a Graphics Processing Unit (GPU), a Tensor Processing Unit, and an Erasure Coding Controller; and

the second device includes a storage device, including a third storage for data and a controller to manage writing the data to the third storage and reading the data from the third storage.

5 . The first device according to claim 4 , wherein the storage device includes a Solid State Drive (SSD).

6 . The first device according to claim 1 , wherein the first device is configured to receive the unique second device ID from the second device.

7 . The first device according to claim 1 , wherein the first device is configured to provide the second device with the unique first device ID.

8 . A method, comprising:

sending a query from a first device to a second device;

receiving a response at the first device from the second device, the response including a first data, the first data identifying the second device;

storing the first data in a second storage in the first device;

accessing a second data from a first storage in the first device, the second data identifying the first device; and

sending the second data from the first device to the second device

wherein the first device is configured to receive a query from an operating system about the first device and the second device and to respond to the query from the operating system with the first data and the second data.

9 . The method according to claim 8 , wherein:

the first device includes a storage device, including a third storage for data and a controller to manage writing the data to the third storage and reading the data from the third storage; and

the second device includes one of a Field Programmable Gate Array (FPGA), a Graphics Processing Unit (GPU), a Tensor Processing Unit, and an Erasure Coding Controller.

10 . The method according to claim 9 , wherein the storage device includes a Solid State Drive (SSD).

11 . The method according to claim 8 , wherein:

the first device includes one of a Field Programmable Gate Array (FPGA), a Graphics Processing Unit (GPU), a Tensor Processing Unit, and an Erasure Coding Controller; and

the second device includes a storage device, including a third storage for data and a controller to manage writing the data to the third storage and reading the data from the third storage.

12 . The method according to claim 11 , wherein the storage device includes a Solid State Drive (SSD).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2023
From: PINTO, OSCAR P.; KACHARE, RAMDAS P.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 064249/0749 →
Continuity (9)
Continuation 16435442 · Jun 7, 2019
Continuation In Part 16260087 · Jan 28, 2019
Continuation In Part 16226629 · Dec 19, 2018
Continuation 16207080 · Nov 30, 2018
Provisional Application 62818096 · Mar 13, 2019
Provisional Application 62745261 · Oct 12, 2018
Provisional Application 62733077 · Sep 18, 2018
Provisional Application 62638040 · Mar 2, 2018
Related Publication 20210303498A1 · Sep 30, 2021
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