IP Library › Granted Patent US 11,320,472
Granted Patent B2
US 11,320,472 · App. 15/698,384 · Granted May 3, 2022

Method for improving EMC robustness of integrated capacitive sensors

Inventors: Reinhard Kauert (Medingen, DE); Martin Schmidt (Dresden, DE)
Assignee: IDT EUROPE GmbH
G01R27/2605G01D3/032G01D5/24G01R31/001H03M1/14H03M1/60
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Quick Facts
Patent No.
US 11,320,472
App. No.
15/698,384
Granted
May 3, 2022
Kind
B2
Abstract

A method is provided for improving the EMC robustness of Integrated Capacitive Sensor systems with a sensor Signal-Conditioner (SSC). The SSC is connected with a capacitive integrating converter to convert a received signal into a bit stream. An oscillator provides a plurality of sampling frequencies. A counter connected with the capacitive integrating converter collects the bit stream and calculates the digital representative of the physical input which is than stored in an output register. The method includes performing some conversions with different sampling frequencies from the oscillator or a frequency divider by the capacitive integrating Signal-Converter; storing the results of the samplings and using the results in the following cycle to calculate for each sampling frequency a difference to the prior sampling of the same frequency; and calculating the digital representative of the input signal from the external sensing capacitor as the reverse weighted average of the samplings of the different frequencies.

Claims (20)

1. A method for improving the EMC robustness of Integrated Capacitive Sensor systems with a sensor Signal-Conditioner, having an external capacitor representing the physical quantity to be sensed, connected with a capacitive integrating converter to convert this capacity into a bit stream and an oscillator providing sampling frequency for the capacitive integrating converter and a counter connected with the capacitive integrating converter, whereby a controller is connected with the counter which collects the bit stream and calculates the digital representative of the physical input which is then stored in an output register, comprising the steps of

performing conversions with different sampling frequencies from the oscillator or a frequency divider by the capacitive Sensor Signal-Converter;

storing the results of the samplings and using the results in the following cycle to calculate for each sampling frequency a difference to the prior sampling of the same frequency; and

calculating the digital representative of the input signal from the external sensing capacitor as the reverse weighted average of the samplings of the different frequencies.

2. The method according claim 1 , further comprising an oscillator generating at least two sampling frequencies with f A =f CLK /(2x) and f B =f CLK /x.

3. The method according claim 2 , further comprising that the at least two different sampling frequencies are generated sequential or parallel.

4. The method according claim 3 , further comprising more conversions with three or other times f A generated by the oscillator or the frequency divider.

5. The method according claim 3 , further comprising that the at least two different sampling frequencies are integer or non-integer shares of the oscillator clock or the frequency divider.

6. The method according one of claim 1 , further comprising that the difference of the last two or more subsequent measurements minus minimum of the differences of the two (or more) frequency channels <A; B; . . . > are used for calculating the digital representative of the input signal.

7. A method, comprising:

receiving a signal into sensor signal conditioner;

sampling the signal in a sampling integrating converter at a plurality of sampling frequencies provided by an oscillator to form sampled signals;

storing the sample signals;

calculating differences between the sample signals and previously sampled signals of the same sampling frequencies;

calculating a reverse weighted average of the samplings at different frequencies from the differences to form a digital representative of the signal; and

storing the digital representative.

8. The method of claim 7 , wherein the oscillator generates at least two sampling frequencies with f A =f CLK /(2x) and f B =f CLK /x.

9. The method of claim 8 , wherein the at least two sampling frequencies are generated sequentially or in parallel.

10. The method of claim 9 , further including conversions with three or other times fA generated by the oscillator or a frequency divider.

11. The method of claim 9 , wherein the at least two different sampling frequencies are integer or non-integer shares of the oscillator.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2019
From: SCHMIDT, MARTIN
To: IDT EUROPE GMBH
Reel/Frame 048398/0819 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2017
From: KAUERT, REINHARD
To: IDT EUROPE GMBH
Reel/Frame 043593/0980 →
Priority Claims (1)
DE 10 2016 117 009.7 · Sep 9, 2016 · national
Continuity (1)
Related Publication 20180074102A1 · Mar 15, 2018
Cited By (1)
US 12,379,231