Method and apparatus for encoding data using a polar code
Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N−K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.
1. A polar encoding method comprising:
encoding, by a device, information bits and at least one parity check bit using a polar code to obtain encoded bits, the polar code associated with a plurality of sub-channels, and the at least one parity check bit being placed in at least one sub-channel of the plurality of sub-channels, wherein the at least one sub-channel is obtained from a segment of a plurality of segments of the plurality of sub-channels based on a minimal weight of the segment of the plurality of segments of the plurality of sub-channels; and
outputting, by the device, the encoded bits obtained from the information bits and the at least one parity check bit.
2. The method of claim 1 , wherein the plurality of sub-channels are ordered based on a reliability metric, and wherein the at least one sub-channel is obtained from the segment of the plurality of segments of the plurality of ordered sub-channels based on the minimal weight.
3. The method of claim 2 , wherein the segment of the plurality of segments of the plurality of ordered sub-channels comprises K sub-channels, where K is an information block length.
4. The method of claim 3 , wherein the at least one sub-channel is obtained from the K sub-channels of the segment of the plurality of segments of the plurality of ordered sub-channels such that:
if a number of sub-channels obtained based on the minimal weight from the K sub-channels is greater than a predetermined value F, F sub-channels are obtained from the K sub-channels based on the minimal weight and in a descending order of the reliability metric.
5. The method of claim 4 , wherein a row-weight of a sub-channel is a number of ones in a row of a Kronecker matrix, the row corresponding to the sub-channel, and the minimal weight being a lowest row-weight of any sub-channel in the K sub-channels.
6. The method of claim 1 , wherein the encoding further comprises, for each sub-channel of the plurality of sub-channels, shifting a cyclic shift register, and:
for an information bit of the information bits, performing an XOR operation with the information bit and a bit of the cyclic shift register; or
for a parity check bit of the at least one parity check bit, retrieving the parity check bit from the cyclic shift register.
7. The method of claim 6 , wherein the cyclic shift register has a length of 5.
8. A device comprising:
an encoder configured to encode information bits and at least one parity check bit using a polar code to obtain encoded bits, the polar code associated with a plurality of sub-channels, and the at least one parity check bit being placed in at least one sub-channel of the plurality of sub-channels, wherein the at least one sub-channel is obtained from a segment of a plurality of segments of the plurality of sub-channels based on a minimal weight of the segment of the plurality of segments of the plurality of sub-channels; and
an interface configured to output the encoded bits obtained from the information bits and the at least one parity check bit.
9. The device of claim 8 , wherein the plurality of sub-channels are ordered based on a reliability metric, and wherein the at least one sub-channel is obtained from the segment of the plurality of segments of the plurality of ordered sub-channels based on the minimal weight.
10. The device of claim 9 , wherein the segment of the plurality of segments of the plurality of ordered sub-channels comprises K sub-channels, where K is an information block length.
11. The device of claim 10 , wherein the at least one sub-channel is obtained from the K sub-channels of the segment of the plurality of segments of the plurality of ordered sub-channels such that:
if a number of sub-channels obtained based on the minimal weight from the K sub-channels is greater than a predetermined value F, F sub-channels are obtained from the K sub-channels based on the minimal weight and in a descending order of the reliability metric.
12. The device of claim 11 , wherein a row-weight of a sub-channel is a number of ones in a row of a Kronecker matrix, the row corresponding to the sub-channel, and the minimal weight being a lowest row-weight of any sub-channel in the K sub-channels.
13. The device of claim 8 , wherein the encoder is further configured to, for each sub-channel of the plurality of sub-channels, shift a cyclic shift register, and:
for an information bit of the information bits, perform an XOR operation with the information bit and a bit of the cyclic shift register; or
for a parity check bit of the at least one parity check bit, retrieve the parity check bit from the cyclic shift register.
14. The device of claim 13 , wherein the cyclic shift register has a length of 5.
15. A device comprising:
a processor; and
a non-transitory computer readable storage medium storing programming for execution by the processor, the programming including instructions to:
encode information bits and at least one parity check bit using a polar code to obtain encoded bits, the polar code associated with a plurality of sub-channels, and the at least one parity check bit being placed in at least one sub-channel of the plurality of sub-channels, wherein the at least one sub-channel is obtained from a segment of a plurality of segments of the plurality of sub-channels based on a minimal weight of the segment of the plurality of segments of the plurality of sub-channels; and
output the encoded bits obtained from the information bits and the at least one parity check bit.
16. The device of claim 15 , wherein the plurality of sub-channels are ordered based on a reliability metric, and wherein the at least one sub-channel is obtained from the segment of the plurality of segments of the plurality of ordered sub-channels based on the minimal weight.
17. The device of claim 16 , wherein the segment of the plurality of segments of the plurality of ordered sub-channels comprises K sub-channels, where K is an information block length.
18. The device of claim 17 , wherein the at least one sub-channel is obtained from the K sub-channels of the segment of the plurality of segments of the plurality of ordered sub-channels such that:
if a number of sub-channels obtained based on the minimal weight from the K sub-channels is greater than a predetermined value F, F sub-channels are obtained from the K sub-channels based on the minimal weight and in a descending order of the reliability metric.
19. The device of claim 18 , wherein a row-weight of a sub-channel is a number of ones in a row of a Kronecker matrix, the row corresponding to the sub-channel, and the minimal weight being a lowest row-weight of any sub-channel in the K sub-channels.
20. The device of claim 15 , wherein the programming further includes instructions to, for each sub-channel of the plurality of sub-channels, shift a cyclic shift register, and:
for encoding an information bit of the information bits, perform an XOR operation with the information bit and a bit of the cyclic shift register; or
for encoding a parity check bit of the at least one parity check bit, retrieve the parity check bit from the cyclic shift register.
21. The device of claim 20 , wherein the cyclic shift register has a length of 5.
22. A decoding method comprising:
receiving, by a device, encoded bits obtained from information bits and of at least one parity check bit; and
decoding the encoded bits using a polar code to obtain the information bits and the at least one parity check bit, the polar code associated with a plurality of sub-channels, and the at least one parity check bit being placed in at least one sub-channel of the plurality of sub-channels, wherein the at least one sub-channel is obtained from a segment of a plurality of segments of the plurality of sub-channels based on a minimal weight of the segment of the plurality of segments of the plurality of sub-channels.
23. The method of claim 22 , wherein the plurality of sub-channels are ordered based on a reliability metric, and wherein the at least one sub-channel is obtained from the segment of the plurality of segments of the plurality of ordered sub-channels based on the minimal weight.
24. The method of claim 23 , wherein the segment of the plurality of segments of the plurality of ordered sub-channels comprises K sub-channels, where K is an information block length.
25. The method of claim 24 , wherein a row-weight of a sub-channel is a number of ones in a row of a Kronecker matrix, the row corresponding to the sub-channel, and the minimal weight being a lowest row-weight of any sub-channel in the K sub-channels.
26. The method of claim 24 , wherein the at least one sub-channel is obtained from the K sub-channels of the segment of the plurality of segments of the plurality of ordered sub-channels such that:
if a number of sub-channels obtained based on the minimal weight from the K sub-channels is greater than a predetermined value F, F sub-channels are obtained from the K sub-channels based on the minimal weight and in a descending order of the reliability metric.
27. The method of claim 22 , wherein the decoding further comprises, for each sub-channel of the plurality of sub-channels, shifting a cyclic shift register, and:
for decoding the encoded bits to obtain an information bit of the information bits, performing an XOR operation with the obtained information bit and a bit of the cyclic shift register; or
for decoding the encoded bits to obtain a parity check bit of the at least one parity check bit, comparing the obtained parity check bit to a bit of the cyclic shift register.
28. The method of claim 27 , wherein the cyclic shift register has a length of 5.