IP Library Granted Patent US 10,211,114
Granted Patent B2
US 10,211,114 · App. 15/702,225 · Granted Feb 19, 2019

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices

Inventors: David J. Corisis (Nampa, ID); Chin Hui Chong (Singapore, SG); Choon Kuan Lee (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L23/053H01L21/56H01L21/561H01L22/10H01L23/3128H01L23/3178H01L23/49805H01L23/49861H01L23/5389H01L24/14H01L24/17H01L24/46H01L24/48H01L24/97H01L25/0657H01L25/074H01L25/105H01L25/117H01L24/16H01L24/45H01L24/49H01L24/73H01L2224/05554H01L2224/16H01L2224/32145H01L2224/32225H01L2224/45144H01L2224/484H01L2224/48011H01L2224/4824H01L2224/48091H01L2224/48227H01L2224/48599H01L2224/4911H01L2224/4912H01L2224/49171H01L2224/73265H01L2224/81H01L2224/85H01L2224/97H01L2225/0651H01L2225/06503H01L2225/06506H01L2225/06524H01L2225/06527H01L2225/06548H01L2225/06586H01L2225/1023H01L2225/1058H01L2225/1064H01L2225/1088H01L2924/00014H01L2924/014H01L2924/01005H01L2924/01006H01L2924/01015H01L2924/01033H01L2924/01046H01L2924/01047H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/10162H01L2924/12042H01L2924/14H01L2924/15184H01L2924/15192H01L2924/15311H01L2924/15331H01L2924/1627H01L2924/181H01L2924/1815H01L2924/19107H01L2924/30105H01L2924/30107
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Quick Facts
Patent No.
US 10,211,114
App. No.
15/702,225
Granted
Feb 19, 2019
Kind
B2
Abstract

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate.

Claims (31)

1. A packaged microelectronic device, comprising:

an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;

a microelectronic die attached and electrically coupled to the interposer substrate via a plurality of wire-bonds, wherein each of the plurality of wire-bonds is in physical contact with one of the plurality of interposer contacts;

a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; and

a plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,

wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate,

wherein each of the plurality of wire-bonds engages one of the plurality of through-casing interconnects at the corresponding interposer contact.

2. The packaged microelectronic device of claim 1 wherein the filament has a height greater than or equal to a thickness of the casing such that at least a portion of each filament is accessible at the top portion of the first casing.

3. The packaged microelectronic device of claim 1 wherein the filaments comprise free-standing wire-bond lines coupled to and projecting from corresponding interposer contacts.

4. The packaged microelectronic device of claim 1 wherein the filaments comprise wire loops attached to and projecting away from corresponding interposer contacts.

5. The packaged microelectronic device of claim 1 , further comprising an electrical coupler coupled to a distal portion of each filament.

6. The packaged microelectronic device of claim 1 wherein:

the die includes an active side, a back side adjacent to the first side of the interposer substrate, a plurality of terminals at the active side, and integrated circuitry electrically coupled to the terminals; and

the terminals are electrically coupled to corresponding interposer contacts via the plurality of wire-bonds.

7. The packaged microelectronic device of claim 1 wherein the device is a known good packaged device.

8. The packaged microelectronic device of claim 1 , further comprising a plurality of electrical couplers attached to corresponding interposer pads.

9. A microelectronic device, comprising:

a support member having a front side with a plurality of support member contacts and a back side opposite the front side, the back side including a plurality of support member pads;

a microelectronic die attached and electrically coupled to the support member via a plurality of terminal connectors, wherein each of the plurality of terminal connectors is coupled to one of the plurality of support member contacts;

an encapsulant covering the die and at least a portion of the support member, wherein the encapsulant has a thickness and a top surface facing away from the support member; and

a plurality of electrically conductive interconnects in contact with and projecting from corresponding support member contacts at the front side of the support member,

wherein the interconnects comprise a plurality of thin, flexible wires attached to and projecting away from the support member contacts in a direction generally normal to the front side of the support member, and

wherein the interconnects extend through the thickness of the encapsulant to a terminus at the top surface of the encapsulant, and

wherein each of the plurality of terminal connectors engages one of the plurality of electrically conductive interconnects at the corresponding support member contact.

10. The microelectronic device of claim 9 wherein the interconnects are inboard of a periphery of the encapsulant such that the interconnects are not accessible along the periphery of the encapsulant.

11. The microelectronic device of claim 9 wherein the microelectronic device is a first microelectronic device, and further comprising one or more second known good packaged devices attached to the first device in a stacked configuration, the individual second devices being electrically coupled to exposed portions of corresponding interconnects at the top surface of the encapsulant.

12. The microelectronic device of claim 9 wherein the plurality of support member pads at the back side of the support member are arranged in an array corresponding to a standard JEDEC pinout.

13. The microelectronic device of claim 9 wherein the microelectronic die is attached and electrically coupled to the support member in a chip-on-board configuration.

14. The microelectronic device of claim 9 , further comprising an electrical coupler coupled to a distal portion of each interconnect at the top surface of the encapsulant.

15. The microelectronic device of claim 9 wherein the interconnects comprise wire loops attached to and projecting away from the corresponding support member contacts.

16. The microelectronic device of claim 9 wherein the device is a known good device, and wherein the device further comprises a plurality of electrical couplers attached to corresponding support member pads at the back side of the support member.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2017
From: CORISIS, DAVID J.; CHONG, CHIN HUI; LEE, CHOON KUAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043563/0411 →
Priority Claims (1)
SG 200601271 · Feb 28, 2006 · national
Continuity (5)
Continuation 15144699 · May 2, 2016
Division 13898004 · May 20, 2013
Division 12689624 · Jan 19, 2010
Continuation 11414864 · May 1, 2006
Related Publication 20180005909A1 · Jan 4, 2018