IP Library Granted Patent US 9,998,032
Granted Patent B2
US 9,998,032 · App. 15/702,228 · Granted Jun 12, 2018

Method of manufacturing a circuit device

Inventors: Shigeaki Mashimo (Maebashi, JP); Fumio Horiuchi (Ashikaga, JP); Kiyoaki Kudo (Gunma, JP); Akira Sakurai (Tatebayashi, JP); Yuhki Inagaki (Kumagaya, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02M7/537H01L21/4825H01L21/56H01L21/565H01L23/293H01L23/3121H01L23/4334H01L23/49531H01L23/49541H01L23/49575H01L24/85H01L25/072H01L25/18H01L25/50H05K1/0203H05K1/181H01L24/45H01L24/48H01L2224/32245H01L2224/45015H01L2224/45124H01L2224/48091H01L2224/48106H01L2224/48137H01L2224/48139H01L2224/48247H01L2224/48472H01L2224/73265H01L2924/1203H01L2924/13055H01L2924/13091H01L2924/14H01L2924/181H01L2924/19105H01L2924/20753Y10T29/4916
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Quick Facts
Patent No.
US 9,998,032
App. No.
15/702,228
Granted
Jun 12, 2018
Kind
B2
Abstract

In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. First and second transistors and first and second diodes are mounted upper surfaces of island portions of respective first and second leads, and are connected to the respective leads through wirings that connect the transistors and diodes to the bonding portions of the respective leads. Lower surfaces of the island portions are attached to an upper surface of a circuit board, and the circuit board, the transistors, the diodes, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin.

Claims (40)

1. A method of manufacturing a circuit device, comprising:

providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion;

mounting a first transistor and a first diode of a first phase on an upper surface of the island portion of a first lead;

connecting the first transistor and the first diode of the first phase to a bonding portion of a second lead by a first wiring;

mounting a second transistor and a second diode of the first phase on the upper surface of the island portion of a third lead;

connecting the second transistor and the second diode of the first phase to a bonding portion of the second lead by a second wiring;

attaching lower surfaces of the island portion of each of the plurality of leads to an upper surface of a circuit board; and

encapsulating by a resin the circuit board, the first and second transistors, the first and second diodes and the lead frame so that the lead portion of each of the plurality of leads are not covered by the resin.

2. The method of claim 1 , further comprising:

mounting a first transistor and a first diode of a second phase on an upper surface of the island portion of a fourth lead;

connecting the first transistor and the first diode of the second phase to the bonding portion of the first lead by a third wiring;

mounting a second transistor and a second diode of the second phase on the upper surface of the island portion of the third lead; and

connecting the second transistor and the second diode of the second phase to a bonding portion of the fourth lead by a fourth wiring.

3. The method of claim 2 , further comprising:

attaching lower surfaces of the island portion of the fourth lead to the upper surface of the circuit board; and

encapsulating by the resin the circuit board, the first and second transistors and first and second diodes of each of the first and second phases, and the lead frame so that the lead portions of the first, second, third, and fourth leads are not covered by the resin.

4. The method of claim 2 , further comprising:

mounting a first transistor and a first diode of a third phase on an upper surface of the island portion of a fifth lead;

connecting the first transistor and the first diode of the third phase to the bonding portion of the first lead by a fifth wiring;

mounting a second transistor and a second diode of the third phase on the upper surface of the island portion of the third lead; and

connecting the second transistor and the second diode of the third phase to a bonding portion of the fifth lead by a fourth wiring.

5. The method of claim 4 , further comprising:

attaching lower surfaces of the island portion of the fourth and fifth leads to the upper surface of the circuit board; and

encapsulating by the resin the circuit board, the first and second transistors and first and second diodes of each of the first, second, and third phases, and the lead frame so that the lead portions of the first, second, third, fourth, and fifth leads are not covered by the resin.

6. The method of claim 5 , further comprising:

mounting an insulative control board on the upper surface of the circuit board; and

mounting a control element on an upper surface of the insulative control board.

7. The method of claim 6 , further comprising:

connecting the control element to the first and second transistors of each of the first, second, and third phases through respective wirings.

8. The method of claim 1 , further comprising:

mounting an insulative control board on the upper surface of the circuit board; and

mounting a control element on an upper surface of the insulative control board.

9. The method of claim 8 , further comprising:

connecting the control element to the first and second transistors of the first phase through respective wirings.

10. The method of claim 1 , further comprising:

connecting a control electrode of the first transistor to a sixth lead of the plurality of leads; and

connecting a control electrode of the second transistor to a seventh lead of the plurality of leads.

11. The method of claim 1 , wherein:

mounting the first transistor on the upper surface of the island portion of the first lead comprises mounting a first insulated gate bipolar transistor (IGBT) on the upper surface of the island portion of the first lead; and

mounting the second transistor on the upper surface of the island portion of the third lead comprises mounting a second IGBT on the upper surface of the island portion of the third lead.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2017
From: MASHIMO, SHIGEAKI; HORIUCHI, FUMIO; KUDO, KIYOAKI; SAKURAI, AKIRA; INAGAKI, YUHKI
To: ON SEMICONDUCTOR TRADING, LTD.
Reel/Frame 043563/0407 →
CHANGE OF NAME Recorded Sep 12, 2017
From: ON SEMICONDUCTOR TRADING LTD.
To: ON SEMICONDUCTOR TRADING SARL
Reel/Frame 043563/0467 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2017
From: ON SEMICONDUCTOR TRADING SARL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 043830/0370 →
Priority Claims (1)
JP 2010-213694 · Sep 24, 2010 · national
Continuity (3)
Division 15003958 · Jan 22, 2016
Division 13242202 · Sep 23, 2011
Related Publication 20180006578A1 · Jan 4, 2018