Semiconductor device
The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.
1. A semiconductor device comprising:
an addition circuit of adding input data and feedback data and outputting addition data;
a first sampling circuit of sampling the addition data from the addition circuit synchronously with a first clock signal and outputting sampling data;
a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data;
a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and
a phase adjustment circuit, when reference data for adjusting a timing of sampling of the first sampling circuit is output as the addition data from the addition circuit, of adjusting phase of the first clock signal so that sampling data output from the first sampling circuit corresponds to the reference data.
2. The semiconductor device according to claim 1 , further comprising a plurality of delay circuits coupled in series and each operating synchronously with the first clock signal,
wherein an output of the first sampling circuit is supplied to the delay circuit in a first stage in the plurality of delay circuits coupled in series, and
wherein the phase adjustment circuit adjusts phase of the first clock signal on the basis of an output of the first sampling circuit and an output of the plurality of delay circuits.
3. The semiconductor device according to claim 1 , further comprising a buffer circuit to which the input data is supplied and which supplies the supplied input data to the addition circuit,
wherein at the time of adjusting a delay time, supply of the input data from the buffer circuit to the addition circuit is stopped, and the feedback data is set as the reference data for adjusting the sampling timing.
4. The semiconductor device according to claim 1 , further comprising a temperature sensor of detecting temperature,
wherein the phase adjustment circuit adjusts the phase of the first clock signal on the basis of temperature data from the temperature sensor.
5. A semiconductor device comprising:
an addition circuit of adding input data and feedback data and outputting addition data;
a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data;
a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data;
a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit;
a temperature sensor of detecting temperature; and
a phase adjustment circuit of changing a timing of sampling of the first sampling circuit on the basis of temperature data from the temperature sensor.