Systems and methods for increasing the transmission speed of a satellite VSAT

1. A satellite terminal, comprising:

circuitry comprising:

a burst formatter configured to burst format an input information signal;

a transmit modulator configured to modulate the input information signal burst formatted by the burst formatter; and

an output configured to output a signal bypassing at least a portion of the transmit modulator, the bypassed signal comprising the input information signal burst formatted by the burst formatter, wherein the circuitry comprises a bypass mode that is activated to bypass the portion of the transmit modulator.

2. The satellite terminal of claim 1 , wherein the circuitry is an application-specific integrated circuit (ASIC).

3. The satellite terminal of claim 2 , wherein the transmit modulator comprises a register, wherein the register is configured to set a multiplexer to output a bypassed signal.

4. The satellite terminal of claim 1 , further comprising:

second circuitry, comprising:

an input coupled to the output and configured to receive a signal bypassing at a least a portion of the transmit modulator; and

a second transmit modulator configured to modulate the bypassed signal.

5. The satellite terminal of claim 4 , wherein the second circuitry further comprises: a registers block configured to apply timing controls to control signals received in a burst segment of the received signal bypassing at least a portion of the transmit modulator, where the timing controls are applied based on at least a transmission symbol rate of the second circuitry.

6. The satellite system of claim 4 , wherein the circuitry comprising the burst formatter is an ASIC and wherein the second circuitry is a field programmable gate array (FPGA).

7. The satellite terminal of claim 2 , wherein the system is a very-small-aperture terminal (VSAT).

8. The satellite terminal of claim 7 , wherein the VSAT comprises an indoor unit and an outdoor unit, and wherein the ASIC is in the indoor unit.

9. The satellite terminal of claim 8 , wherein the circuitry further comprises an ASIC outdoor unit control (ODUC) signal block, and wherein the second circuitry further comprises an FPGA outdoor unit control (ODUC) signal block coupled to an output of the ASIC ODUC signal block.

10. The satellite terminal of claim 4 , further comprising a digital-to-analog converter (DAC) comprising an input and output, wherein the DAC input is coupled to an output of the second circuitry, and wherein the DAC output is coupled to a block upconverter (BUC).

11. The satellite terminal of claim 1 , wherein the bypassed signal comprises burst segments comprising data signals and control signals.

12. A method, comprising:

determining whether to bypass a transmit modulator of a first circuitry;

based on the determination, setting the first circuitry to a bypass mode or a regular mode;

using a first circuitry to burst format an input information signal with a payload burst segment;

if the first circuitry is set to a bypass mode, the burst formatted input information signal bypassing the transmit modulator; and

if the first circuitry is set to a regular mode, modulating the burst formatted input information signal using the transmit modulator of the first circuitry.

13. The method of claim 12 , further comprising:

setting the first circuitry to the bypass mode; and

the burst-formatted input information signal bypassing the transmit modulator.

14. The method of claim 13 , further comprising: using a transmit modulator of a second circuitry to modulate the bypassed burst-formatted input information signal.

15. The method of claim 13 , further comprising: using second circuitry to insert additional burst segments into the bypassed burst-formatted input information signal.

16. The method of claim 15 , wherein the additional burst segments comprise at least one of a unique word (UW) segment, a ramp up segment, a ramp down segment, or a pilot segment.

17. The method of claim 13 , wherein the first circuitry is an application-specific integrated circuit (ASIC).

18. The method of claim 17 , wherein the ASIC is an ASIC of a satellite terminal.

19. The method of claim 14 , wherein the first circuitry is an ASIC of a satellite terminal and wherein the second circuitry is a field programmable gate array (FPGA) of the satellite terminal.

20. A method, comprising:

using first circuitry to burst format an input information signal with burst segments comprising a data signal and a control signal;

the burst-formatted input information signal bypassing at least a portion of a transmit modulator of the first circuitry; and

using second circuitry to insert additional burst segments into the bypassed, burst-formatted input information signal.

21. The method of claim 20 , further comprising: using a transmit modulator of the second circuitry to modulate the bypassed, burst-formatted input information signal.

22. The method of claim 21 , wherein the additional burst segments comprise at least two of a unique word (UW) segment, a ramp up segment, a ramp down segment, or a pilot segment.

23. The method of claim 21 , further comprising: the second circuitry applying timing controls to the control signals of the burst segments, where the timing controls are applied based on at least a transmission symbol rate of the second circuitry.

24. The method of claim 21 , wherein the first circuitry is an ASIC of a satellite terminal and wherein the second circuitry is a component of the satellite terminal.

25. The method of claim 24 , wherein the second circuitry is an FPGA of the satellite terminal.

26. The method of claim 21 , wherein the control signal comprises a burst transmission timing signal.

27. The method of claim 21 , wherein the control signal comprises a burst information signal comprising burst information of at least one of: a modulation type of a current burst or a symbol rate of a current burst.