IP Library › Granted Patent US 10,528,414
Granted Patent B2
US 10,528,414 · App. 15/702,853 · Granted Jan 7, 2020

Centralized error handling in application specific integrated circuits

Inventors: Andrew John Tomlin (San Jose, CA); Justin Cree Jones (Burlingame, CA)
Assignee: Toshiba Memory Corporation
G06F11/0784G06F11/0751G06F11/0793
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,528,414
App. No.
15/702,853
Granted
Jan 7, 2020
Kind
B2
Abstract

In one embodiment, a system comprises a plurality of hardware blocks, each of the plurality of hardware blocks configured to perform a function in response to a request associated with a command, an error queue manager configured to receive an error message from at least one of the plurality of hardware blocks and store the error message in an error queue, the error message including a command identifier of a command in error, and an error state manager including an error state bitmap, the error state bitmap storing an error state bit for each of a plurality of command identifiers, the error state bit indicating either command in error or command not in error; the error state manager configured to set the error state bit for the command identifier of the command in error to indicate command in error in response to an error state message, the error state message including the command identifier of the command in error.

Claims (36)

1. A system comprising:

a plurality of hardware blocks, each of the plurality of hardware blocks configured to perform a function in response to a request associated with a command;

an error queue manager configured to receive an error message from at least one of the plurality of hardware blocks and store the error message in an error queue, the error message including a command identifier of a command in error; and

an error state manager including an error state bitmap, the error state bitmap storing an error state bit for each of a plurality of command identifiers, the error state bit indicating either command in error or command not in error;

the error state manager configured to set the error state bit for the command identifier of the command in error to indicate command in error in response to an error state message, the error state message including the command identifier of the command in error.

2. The system of claim 1 , wherein each of the plurality of hardware blocks is configured to send a query to the error state manager to determine the error state of a command prior to performing a function in response to a request associated with the command.

3. The system of claim 2 , wherein each of the plurality of hardware blocks is configured to disregard a request to perform a function associated with a command in error.

4. The system of claim 1 , wherein the error queue manager is further configured to send the error state message to the error state manager.

5. The system of claim 1 , wherein each of the plurality of hardware blocks is further configured to send the error state message to the error state manager.

6. The system of claim 1 , wherein each of the plurality of hardware blocks is configured to detect an error in performing the function associated with the request and send the error message to the error queue manager upon detection of the error.

7. The system of claim 6 , wherein each of the plurality of hardware blocks is a state machine and is further configured to release all state related to the request after sending the error message to the error queue manager.

8. The system of claim 1 , further comprising firmware configured to retrieve the error message from the error queue in the error queue manager and to identify a resource in at least one of the plurality of hardware blocks allocated to a request including the command identifier of the command in error.

9. The system of claim 8 , wherein the firmware is further configured to instruct the at least one of the plurality of hardware blocks to release the resource allocated to the request including the command identifier of the command in error.

10. The system of claim 9 , wherein the firmware is further configured to instruct the error state manager to set the error state bit in the error state bitmap for the command identifier as command not in error when all resources allocated to the request in the plurality of hardware blocks have been released.

11. The system of claim 1 , wherein the error message further includes an identifier of the at least one of the plurality of hardware blocks.

12. The system of claim 1 , wherein the error message further includes state information for the at least one of the plurality of hardware blocks.

13. A method comprising:

receiving an error message in an error queue manager from one of a plurality of hardware blocks, the error message including a command identifier;

storing the error message in an error queue;

causing an error state manager to set an error state bit in an error state bitmap corresponding to the command identifier as command in error;

reporting presence of the error message in the error queue to firmware;

identifying at least one resource associated with the command identifier in a second one of the plurality of hardware blocks by the firmware; and

causing the second one of the plurality of hardware blocks to release the at least one resource associated with the command identifier.

14. The method of claim 13 , further comprising querying the error state manager to determine the error state of a command by one of the plurality of hardware blocks.

15. The method of claim 13 , further comprising

reporting the error state of a command in response to a query from one of the plurality of hardware blocks;

if the error state of the command is command in error, disregarding a request associated with the command; and

if the error state of the command is command not in error, performing a function in response to the request associated with the command.

16. The method of claim 13 , wherein causing an error state manager to set an error state bit in an error state bitmap corresponding to the command identifier as command in error comprises sending an error state message to the error state manager from either the error queue manager or the one of the plurality of hardware blocks.

17. The method of claim 13 , further comprising causing the error state manager to set the error state bit in an error state bitmap corresponding to the command identifier as command not in error when the at least one resource associated with the command identifier has been released.

18. The method of claim 13 , further comprising detecting an error in performing a function associated with the command identifier by the one of a plurality of hardware blocks and releasing all state information related to the error in the one of a plurality of hardware blocks.

19. The method of claim 13 , wherein each of the plurality of hardware blocks is a state machine and is configured to release all state related to the command identifier after sending the error message to the error queue manager.

20. The method of claim 13 , wherein the plurality of hardware blocks comprise an application specific integrated circuit, the application specific integrated circuit storing the firmware in a memory.

21. The method of claim 13 , further comprising sending a command completion message to a host system, the command completion message including an error code.

22. The method of claim 13 , wherein the error message further includes an identifier of the one of the plurality of hardware blocks.

23. The method of claim 13 , wherein the error message further includes state information for the one of the plurality of hardware blocks.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2018
From: TOMLIN, ANDREW J.; JONES, JUSTIN CREE
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Reel/Frame 046379/0767 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2018
From: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 046379/0831 →
Continuity (1)
Related Publication 20190079824A1 · Mar 14, 2019