IP Library Granted Patent US 10,379,154
Granted Patent B2
US 10,379,154 · App. 15/703,319 · Granted Aug 13, 2019

Testing system and method

Inventors: Benjamin Brown (Palo Alto, CA); Niraj Rangwala (San Jose, CA); David McConnell (Oakland, CA); Howard Massenn (Milpitas, CA)
Assignee: Xcerra Corporation
G01R31/2834G01R1/07378G01R1/07385G01R19/25G01R31/31924
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Quick Facts
Patent No.
US 10,379,154
App. No.
15/703,319
Granted
Aug 13, 2019
Kind
B2
Abstract

A method, computer program product, computing system, and an automated test platform for testing at least one device under test includes a test head configured to receive the at least one device under test. A processing system is configured to: provide a voltage signal having a plurality of voltages to the at least one device under test, and monitor a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages. The plurality of monitored current values are stored.

Claims (36)

1. An automated test platform for testing at least one device under test, the automated test platform comprising:

a test head configured to receive the at least one device under test;

a processing system configured to:

provide a voltage signal having a plurality of voltages to the at least one device under test, wherein the voltage signal having the plurality of voltages is a temporally-defined voltage signal having a plurality of voltages, wherein an amplitude and a duration are defined for each of the plurality of voltages,

monitor a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages, and

store the plurality of monitored current values.

2. The automated test platform of claim 1 further comprising:

an interconnection platform configured to couple the processing system and the test head.

3. The automated test platform of claim 1 further comprising:

an adapter board configured to couple the at least one device under test to the test head.

4. The automated test platform of claim 3 wherein the at least one device under test includes a plurality of devices under test.

5. The automated test platform of claim 4 wherein the adapter board is configured to couple the plurality of devices under test to the test head.

6. The automated test platform of claim 1 wherein the processing system includes:

a variable voltage source configured to provide the voltage signal having the plurality of voltages to the at least one device under test.

7. The automated test platform of claim 6 wherein the processing system further includes:

a current monitoring system configured to define the plurality of monitored current values that correspond to the plurality of voltages.

8. The automated test platform of claim 7 wherein the current monitoring system further includes:

a current monitoring circuit for generating an analog representation of the plurality of monitored current values.

9. The automated test platform of claim 8 wherein the current monitoring system further includes:

a current conversion circuit configured to convert the analog representation of the plurality of monitored current values into a digital representation of the plurality of monitored current values.

10. The automated test platform of claim 1 wherein the plurality of monitored current values is temporally aligned with the temporally-defined voltage signal.

11. A computer-implemented method, executed on a computing device, the computer-implemented method comprising:

providing a voltage signal having a plurality of voltages to at least one device under test, wherein the voltage signal having the plurality of voltages is a temporally-defined voltage signal having a plurality of voltages, wherein an amplitude and a duration are defined for each of the plurality of voltages,

monitoring a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages, and

storing the plurality of monitored current values.

12. The computer-implemented method of claim 11 wherein the plurality of monitored current values is temporally aligned with the temporally-defined voltage signal.

13. A computing system including a processor and memory configured to perform operations comprising:

providing a voltage signal having a plurality of voltages to at least one device under test, wherein the voltage signal having the plurality of voltages is a temporally-defined voltage signal having a plurality of voltages, wherein an amplitude and a duration are defined for each of the plurality of voltages,

monitoring a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages, and

storing the plurality of monitored current values.

14. The computing system of claim 13 wherein the plurality of monitored current values is temporally aligned with the temporally-defined voltage signal.

15. An apparatus comprising:

means for providing a voltage signal having a plurality of voltages to at least one device under test, wherein the voltage signal having the plurality of voltages is a temporally-defined voltage signal having a plurality of voltages, wherein an amplitude and a duration are defined for each of the plurality of voltages,

means for monitoring a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages, and

means for storing the plurality of monitored current values.

16. The apparatus of claim 15 wherein the plurality of monitored current values is temporally aligned with the temporally-defined voltage signal.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 047185, FRAME 0624 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: XCERRA CORPORATION
Reel/Frame 066762/0811 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047185 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 28, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047675/0354 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2018
From: BROWN, BENJAMIN; RANGWALA, NIRAJ; MCCONNELL, DAVID; MAASSEN, HOWARD
To: XCERRA CORPORATION
Reel/Frame 047564/0963 →
PATENT SECURITY AGREEMENT Recorded Oct 2, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047185/0624 →
Continuity (2)
Provisional Application 62395806 · Sep 16, 2016
Related Publication 20180080978A1 · Mar 22, 2018