IP Library Granted Patent US 10,153,015
Granted Patent B2
US 10,153,015 · App. 15/703,589 · Granted Dec 11, 2018

Managing disturbance induced errors

Inventors: Prashant S. Damle (Santa Clara, CA); Frank T. Hady (Portland, OR); Paul D. Ruby (Folsom, CA); Kiran Pangal (Fremont, CA); Sowmiya Jayachandran (Portland, OR)
Assignee: Intel Corporation
G11C7/1072G11C11/406G11C11/40618G11C16/3431
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Quick Facts
Patent No.
US 10,153,015
App. No.
15/703,589
Granted
Dec 11, 2018
Kind
B2
Abstract

In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Claims (70)

1. A method comprising:

determining, by processing logic, that one or more neighboring memory cells associated with a target memory cell are to be refreshed;

generating a command associated with refreshing the one or more neighboring memory cells, the command including an identifier that identifies the target memory cell; and

sending the command to a memory device that includes the target memory cell and the one or more neighboring memory cells.

2. The method of claim 1 , wherein the command to direct the memory device to refresh the one or more neighboring memory cells.

3. The method of claim 1 , wherein the command to direct the memory device to return one or more addresses associated with the one or more neighboring memory cells.

4. The method of claim 3 , further comprising:

receiving the one or more addresses associated with the one or more neighboring memory cells from the memory device responsive to the memory device receiving the command.

5. The method of claim 4 , further comprising:

causing the one or more neighboring memory cells associated with the received one or more addresses to be refreshed.

6. The method of claim 4 , wherein the one or more neighboring memory cells associated with the received one or more addresses are refreshed by rewriting the one or more neighboring memory cells with information that is stored in the one or more neighboring memory cells.

7. The method of claim 1 , wherein the determining further comprises:

generating a random number for an access of the target memory cell;

determining whether the generated random number matches a predefined number; and

causing the one or more neighboring memory cells to be refreshed if the generated random number matches the predefined number.

8. The method of claim 1 , wherein the determining further comprises:

maintaining a count associated with accessing the target memory cell;

determining whether the maintained count matches a predefined count; and

causing the one or more neighboring memory cells to be refreshed if the maintained count matches the predefined count.

9. At least one non-transitory machine readable medium comprising a plurality of instructions that in response to being executed by a system cause the system to:

determine that one or more neighboring memory cells associated with a target memory cell are to be refreshed;

generate a command associated with refreshing the one or more neighboring memory cells, the command including an identifier that identifies the target memory cell; and

send the command to a memory device that includes the target memory cell and the one or more neighboring memory cells.

10. The at least one non-transitory machine readable medium of claim 9 , wherein the command to direct the memory device to refresh the one or more neighboring memory cells.

11. The at least one non-transitory machine readable medium of claim 9 , wherein the command to direct the memory device to return one or more addresses associated with the one or more neighboring memory cells.

12. The at least one non-transitory machine readable medium of claim 11 , the instructions to further cause the system to:

receive the one or more addresses associated with the one or more neighboring memory cells from the memory device responsive to the memory device receiving the command.

13. The at least one non-transitory machine readable medium of claim 12 , the instructions to further cause the system to:

cause the one or more neighboring memory cells associated with the received one or more addresses to be refreshed.

14. The at least one non-transitory machine readable medium of claim 13 , comprising the instructions to further cause the system to:

cause the one or more neighboring memory cells associated with the received one or more addresses to be refreshed via a rewrite of the one or more neighboring memory cells with information that is stored in the one or more neighboring memory cells.

15. The at least one non-transitory machine readable medium of claim 9 , the instructions to cause the system to determine that one or more neighboring memory cells associated with a target memory cell are to be refreshed further comprises the system to:

generate a random number for an access of the target memory cell;

determine whether the generated random number matches a predefined number;

and cause the one or more neighboring memory cells to be refreshed if the generated random number matches the predefined number.

16. The at least one non-transitory machine readable medium of claim 9 , the instructions to cause the system to determine that one or more neighboring memory cells associated with a target memory cell are to be refreshed further comprises the system to:

maintain a count associated with accessing the target memory cell;

determine whether the maintained count matches a predefined count; and

cause the one or more neighboring memory cells to be refreshed if the maintained count matches the predefined count.

17. An apparatus comprising:

a command bus interface; and

a controller to include processing logic, the processing logic to:

determine that one or more neighboring memory cells associated with a target memory cell are to be refreshed;

generate a command associated with refreshing the one or more neighboring memory cells, the command including an identifier that identifies the target memory cell; and

send the command to a memory device through the command bus interface, the command to include the target memory cell and the one or more neighboring memory cells.

18. The apparatus of claim 17 , wherein the command to direct the memory device to refresh the one or more neighboring memory cells.

19. The apparatus of claim 17 , wherein the command to direct the memory device to return one or more addresses associated with the one or more neighboring memory cells.

20. The apparatus of claim 19 , wherein the processing logic to further:

receive the one or more addresses associated with the one or more neighboring memory cells from the memory device responsive to the memory device receiving the command.

21. The apparatus of claim 20 , wherein the processing logic to further:

cause the one or more neighboring memory cells associated with the received one or more addresses to be refreshed.

22. The apparatus of claim 20 , wherein the processing logic to further:

cause the one or more neighboring memory cells associated with the received one or more addresses to be refreshed via a rewrite of the one or more neighboring memory cells with information that is stored in the one or more neighboring memory cells.

23. The apparatus of claim 17 , wherein the processing logic to determine that one or more neighboring memory cells associated with a target memory cell are to be refreshed further comprises:

generate a random number for an access of the target memory cell;

determine whether the generated random number matches a predefined number; and

cause the one or more neighboring memory cells to be refreshed if the generated random number matches the predefined number.

24. The apparatus of claim 17 , wherein the processing logic to determine that one or more neighboring memory cells associated with a target memory cell are to be refreshed further comprises:

maintain a count associated with accessing the target memory cell;

determine whether the maintained count matches a predefined count; and

cause the one or more neighboring memory cells to be refreshed if the maintained count matches the predefined count.

25. A system comprising:

a memory device; and

a controller to include processing logic, the processing logic to:

determine that one or more neighboring memory cells associated with a target memory cell are to be refreshed;

generate a command associated with refreshing the one or more neighboring memory cells, the command including an identifier that identifies the target memory cell; and

send the command to a memory device, the command to include the target memory cell and the one or more neighboring memory cells.

26. The system of claim 25 , wherein the command to cause the memory device to refresh the one or more neighboring memory cells.

27. The system of claim 25 , wherein the command to cause the memory device to return one or more addresses associated with the one or more neighboring memory cells.

28. The system of claim 25 , wherein the memory device further comprises one or more memory arrays that include volatile memory or non-volatile memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072890/0340 →
Continuity (3)
Continuation 14938221 · Nov 11, 2015
Continuation 13832278 · Mar 15, 2013
Related Publication 20180068695A1 · Mar 8, 2018