Radio-frequency amplifier having active gain bypass circuit
Radio-frequency (RF) amplifier having active gain bypass circuit. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.
1. A radio-frequency amplifier comprising:
a first amplification path implemented to amplify a signal, and including a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode;
a second amplification path implemented to provide a second gain for the signal when in a second mode, the second amplification path including a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path;
a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode; and
an inter-stage switch implemented between the respective input transistor and the cascode transistor of each of the first and second amplification paths.
2. The radio-frequency amplifier of claim 1 wherein the first gain is greater than the second gain.
3. The radio-frequency amplifier of claim 2 wherein the switch is implemented to be a part of the second amplification path.
4. The radio-frequency amplifier of claim 3 wherein the second amplification path further includes an attenuator in series with the switch, and configured to facilitate the second gain of the second mode.
5. The radio-frequency amplifier of claim 3 wherein the second amplification path further includes a matching network in series with the switch.
6. The radio-frequency amplifier of claim 3 wherein the first amplification path and the second amplification path share a common input node.
7. The radio-frequency amplifier of claim 3 wherein the first amplification path and the second amplification path have separate input nodes.
8. The radio-frequency amplifier of claim 3 wherein each of the first input transistor, the second input transistor, and the cascode transistor is implemented as a field-effect transistor having a gate, a source, and a drain.
9. The radio-frequency amplifier of claim 8 wherein each of the first input transistor, the second input transistor, the cascode transistor, and the switch of the second amplification path is implemented as a silicon-on-insulator device.
10. The radio-frequency amplifier of claim 8 wherein the gate of each of the first input transistor and the second input transistor is configured to receive the signal, the drain of each of the first input transistor and the second input transistor is coupled to the source of the cascode transistor, and the source of each of the first input transistor and the second input transistor is inductively coupled to ground.
11. The radio-frequency amplifier of claim 10 wherein the drain of the cascode transistor is coupled to an output node of the radio-frequency amplifier and configured to receive a supply voltage.
12. The radio-frequency amplifier of claim 10 wherein the source of the first input transistor and the source of the second input transistor are inductively coupled to ground through a common degeneration inductance.
13. The radio-frequency amplifier of claim 10 wherein the source of the first input transistor and the source of the second input transistor are inductively coupled to ground through separate degeneration inductances.
14. The radio-frequency amplifier of claim 3 wherein the radio-frequency amplifier is a low-noise amplifier.
15. The radio-frequency amplifier of claim 14 wherein the switch of the second amplification path is configured to provide a reduced level of parasitic capacitance when in an OFF state in the first mode.
16. The radio-frequency amplifier of claim 15 wherein the first amplification path is configured to provide the first gain for a weak received signal, such that the amplified signal includes a desired combination of the first gain and a low noise figure.
17. The radio-frequency amplifier of claim 15 wherein the second amplification path is configured to provide the second gain for a strong received signal, such that the amplified signal includes a desired combination of the second gain and a high linearity level.
18. A semiconductor die having a radio-frequency circuit, comprising:
a substrate; and
an amplifier implemented on the substrate, the amplifier including a first amplification path implemented to amplify a signal and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode, the amplifier further including a second amplification path implemented to provide a second gain for the signal when in a second mode, the second amplification path including a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path, the amplifier further including a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode, the amplifier further including an inter-stage switch implemented between the respective input transistor and the cascode transistor of each of the first and second amplification paths.
19. A radio-frequency module comprising:
a packaging substrate configured to receive a plurality of components; and
an amplifier implemented on the packaging substrate, the amplifier including a first amplification path implemented to amplify a signal and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode, the amplifier further including a second amplification path implemented to provide a second gain for the signal when in a second mode, the second amplification path including a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path, the amplifier further including a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode, the amplifier further including an inter-stage switch implemented between the respective input transistor and the cascode transistor of each of the first and second amplification paths.