IP Library › Granted Patent US 10,276,690
Granted Patent B2
US 10,276,690 · App. 15/705,034 · Granted Apr 30, 2019

Semiconductor device and method

Inventors: Shih-Hang Chiu (Taichung, TW); Chung-Chiang Wu (Taichung, TW); Chia-Ching Lee (New Taipei, TW); Da-Yuan Lee (Jhubei, TW); Ching-Hwanq Su (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/66795H01L21/225H01L21/28088H01L21/28185H01L21/3065H01L21/76224H01L29/66492H01L29/66545H01L21/31053H01L29/6656
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Quick Facts
Patent No.
US 10,276,690
App. No.
15/705,034
Granted
Apr 30, 2019
Kind
B2
Abstract

A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).

Claims (48)

1. A method comprising:

forming a dummy gate structure over a semiconductor fin;

forming a dielectric layer on opposing sides of the dummy gate structure;

removing the dummy gate structure to form a recess in the dielectric layer;

forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess; and

treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F), wherein treating the gate dielectric layer comprises:

forming a fluoride-containing film over the at least one conductive layer; and

driving fluoride in the fluoride-containing film into the gate dielectric layer.

2. The method of claim 1 , wherein the forming the gate dielectric layer and the at least one conductive layer comprises:

forming a gate dielectric layer over the sidewalls and the bottom of the recess;

forming a capping layer over the gate dielectric layer, the capping layer comprising a first conductive material; and

forming a barrier layer over the capping layer, the barrier layer comprising a second conductive material different from the first conductive material.

3. The method of claim 2 , wherein the gate dielectric layer comprise a high-K dielectric material.

4. The method of claim 3 , wherein the capping layer comprises titanium nitride (TiN), and the barrier layer comprises tantalum nitride (TaN).

5. The method of claim 1 , further comprising performing a thermal anneal process after the treating.

6. The method of claim 1 , further comprising filling the recess using a conductive material after the treating.

7. A method of forming a Fin Field-Effect Transistor (FinFET) comprising:

providing a substrate with a fin protruding above upper surfaces of isolation structures disposed on opposing sides of the fin;

forming a first gate structure over the fin;

forming an inter-layer dielectric (ILD) layer around the first gate structure, the ILD layer exposing an upper surface of the first gate structure;

removing the first gate structure to form a recess in the ILD layer;

forming a layer slack in the recess, wherein the forming the layer stack comprises:

conformally forming a high-K dielectric layer in the recess;

conformally forming a conductive capping layer over the high-K dielectric layer; and

conformally forming a conductive barrier layer over the conductive capping layer;

performing a surface treatment process for the layer stack using a chemical comprising fluoride, wherein the surface treatment process drives fluoride into the high-K dielectric layer, wherein performing the surface treatment process comprises:

soaking the layer stack in a fluoride-containing gas or a fluoride-containing plasma; and

depositing a film over the conductive barrier layer after the making using a fluoride-containing precursor; and

performing a thermal anneal process after the surface treatment process.

8. The method of claim 7 , further comprising:

removing the film after the thermal anneal process; and

filling the recess with a conductive material.

9. A method comprising:

forming a dielectric layer;

covering the dielectric layer with at least one conductive layer;

supplying a fluoride-containing precursor over the at least one conductive layer, wherein the supplying deposits a film over the at least one conductive layer; and

driving fluoride of the fluoride-containing precursor into the dielectric layer.

10. The method of claim 9 , wherein the fluoride-containing precursor is a fluoride-containing gas or a fluoride-containing plasma.

11. The method of claim 9 , wherein the dielectric layer comprises a high-K dielectric material, and wherein the driving comprises at least a thermal drive-in process.

12. The method of claim 1 , wherein forming the fluoride-containing film comprises forming the fluoride-containing film using a fluoride-containing precursor.

13. The method of claim 12 , wherein the fluoride-containing precursor comprises molybdenum hexafluoride (MoF 6 ).

14. The method of claim 12 , wherein fluoride in the fluoride-containing film is driven into the gate dielectric layer but not into the dielectric layer.

15. The method of claim 1 , further comprising, after treating the gate dielectric layer, removing the fluoride-containing film.

16. The method of claim 9 , further comprising removing the film after the driving.

17. The method of claim 9 , where the supplying comprises soaking the at least one conductive layer in a gas comprising tungsten hexafluoride (WF 6 ).

18. The method of claim 9 , where the supplying comprises treating the at least one conductive layer with a plasma process using nitrogen trifluoride (NF 3 ).

19. The method of claim 7 , further comprising removing the film after performing the thermal anneal process.

20. The method of claim 7 , further comprising after performing the thermal anneal process, forming a conductive material directly on the film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2017
From: CHIU, SHIH-HANG; WU, CHUNG-CHIANG; LEE, CHIA-CHING; LEE, DA-YUAN; SU, CHING-HWANQ
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 043629/0388 →
Continuity (2)
Provisional Application 62539214 · Jul 31, 2017
Related Publication 20190035916A1 · Jan 31, 2019