Single interconnect index pointer for stacked die address encoding

1. A method for automatically identifying integrated circuits of a stack of integrated circuits using a single thru-chip via location of the stack of integrated circuits, the method comprising:

powering up a newly assembled stack of integrated circuits;

pulling a single auto-identify output terminal of a plurality of the integrated circuits of the stack of integrated circuits to a first logic state;

receiving a reset signal at an integrated circuit of the stack;

in response to the reset signal and when a single, auto-identify input terminal of a first integrated circuit of the stack of integrated circuits is at a second logic level, setting an internal indicator of the first integrated circuit to a “master” state, and releasing the single auto-identify output terminal from the first logic state; and

in response to the reset signal and when the single, auto-identify input terminal of the first integrated circuit of the stack of integrated circuits is at the first logic state, setting the internal indicator of the first integrated circuit to a “common” state.

2. The method of claim 1 , wherein the internal indicator is a first stack address of the first integrated circuit of the stack of integrated circuits.

3. The method of claim 1 , including when the single, auto-identify input terminal of the first integrated circuit of the stack of integrated circuits transition from the first logic state to a second logic state, setting the internal indicator of the first integrated circuit from a “common” state to a “unique” state.

4. The method of claim 1 , wherein the state of the internal indicator of each integrated circuit of the stack of integrated circuits is a first stack address of the integrated circuit.

5. The method of claim 1 , including receiving and storing a soft address at the first integrated circuit, the soft address indicative of a second stack address of the first integrated circuit.

6. The method of claim 5 , including receiving a command to index a next chip at the first integrated circuit;

setting the internal indicator of the first integrated circuit to the “common” state in response to the command to index to a next integrated circuit; and

releasing the single auto-identify output terminal of the first integrated circuit from the first logic state.

7. The method of claim 1 , including sequentially setting the internal indicator of each integrated circuit of the stack, except a master integrated circuit of the stack, to a “unique” state.

8. The method of claim 7 , including, while the internal indicator of a particular integrated circuit of the stack of integrated circuits is in the “unique” state, responding at the particular integrated circuit to commands having an address corresponding to the internal indicator.

9. The method of claim 8 , including, while the internal indicator of the particular integrated circuit of the stack of integrated circuits is in the “unique” state, receiving a command to establish a second stack address.

10. The method of claim 9 , receiving a command at one or more of the integrated circuits of the stack of integrated circuits to use the second stack address as a primary address of the integrated circuit.

11. An integrated circuit configured to stack with a plurality of other integrated circuits, the integrated circuit comprising:

a single auto-identify input terminal;

a single auto-identify output terminal; and

control logic configured:

to receive a logic state on the single auto-identify input terminal;

to set an internal indicator to one of at least three states, and

to control a state of the single auto-identify output terminal in response to a power up condition or in response to a change in the logic state of the single auto-identify input terminal; and

wherein functions of the integrated circuit can be initiated using an address associated with the state of the internal indicator.

12. The integrated circuit of claim 11 , wherein, in response to the power up condition, the control logic is configured to pull the auto-identify output to a first state.

13. The integrated circuit of claim 12 , wherein in response to a power-up reset, and in response to the single auto-identify input in a second state, the control logic is configured to set the internal indicator to a “master” state.

14. The integrated circuit of claim 13 , wherein in response to the power-up reset, and in response to the single auto-identify input in the first state, the control logic is configured to set the internal indicator to a “common” state.

15. The integrated circuit of claim 13 , wherein in response to the internal indicator in the “master” state, the control logic is configured to release the pull down of the auto-identify ratioed output.

16. The integrated circuit of claim 11 , wherein the control logic, in response to the change in logic state of the single auto-identify input, changes the internal indicator from a “common” state to a “unique” state.

17. The integrated circuit of claim 11 , wherein a value of the internal indicator provides an address of the integrated circuit; and

wherein the control logic is configured to respond to commands when the address of the integrated circuit is received via a command/address bus of the integrated circuit.

18. The integrated circuit of claim 17 , including a second internal indicator configured to store a second address of the integrated circuit.

19. The integrated circuit of claim 11 , wherein the integrated circuit is a memory circuit.

20. A system comprising:

a plurality of integrated circuits arranged in a stack, each integrated circuit comprising:

a single auto-identify input terminal;

a single auto-identify output terminal; and

control logic configured to receive a logic state on the single auto-identify input terminal; to set an internal indicator to one of three states, and to control a state of the single auto-identify output terminal in response to a power up condition or to a change in the logic state of the single auto-identify input terminal; and

wherein the single auto-identify input terminal, or the single auto-identify output terminal, of each integrated circuit of the stack is coupled to the single auto-identify input terminal, or the single auto-identify output, of another integrated circuit of the stack.

21. The system of claim 20 , wherein the stack of integrated circuits include a plurality of memory integrated circuits.

22. The system of claim 21 , wherein the stack of integrated circuits include a memory interface integrated circuit.