IP Library › Granted Patent US 10,359,769
Granted Patent B2
US 10,359,769 · App. 15/706,209 · Granted Jul 23, 2019

Substrate routing and throughput modeling

Inventor: Shyam Sunder Emani (Cupertino, CA)
Assignee: Applied Materials, Inc.
G05B19/41885G05B19/41865H01L21/67167H01L21/67184H01L21/67276G05B2219/32247G05B2219/42155G05B2219/45031H01L21/28185H01L21/67207
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Quick Facts
Patent No.
US 10,359,769
App. No.
15/706,209
Granted
Jul 23, 2019
Kind
B2
Abstract

Embodiments disclosed herein generally relate to methods, systems, and non-transitory computer readable medium for scheduling a substrate processing sequence in an integrated substrate processing system. A client device assigns a processing sequence to each substrate in a batch of substrates to be processed. The client device assigns a processing chamber to each process in the process sequence for each processing chamber in the integrate substrate processing system. The client device generates a processing model for the batch of substrates. The processing model defines a start time for each substrate in each processing chamber. The client device generates a timetable for the batch of semiconductor substrates based off the processing model. The client device processes the batch of substrates in accordance with the timetable.

Claims (57)

1. A method of scheduling a semiconductor substrate processing sequence in an integrated substrate processing system, comprising:

assigning a processing sequence to each semiconductor substrate in a batch of semiconductor substrates to be processed;

for each processing chamber in the integrated substrate processing system, assigning a processing chamber to each process in the processing sequence;

generating a processing model for the batch of semiconductor substrates, wherein the processing model defines a start time for each substrate in each processing chamber;

generating a timetable for the batch of semiconductor substrates based off the processing model; and

processing the batch of semiconductor substrates in accordance with the timetable.

2. The method of claim 1 , wherein the processing sequence is the same for each semiconductor substrate in the batch.

3. The method of claim 1 , wherein the processing sequence is not the same for each semiconductor substrate in the batch.

4. The method of claim 3 , wherein assigning the processing sequence to each semiconductor substrate in the batch of semiconductor substrates to be processed, comprises:

selecting a first semiconductor substrate and a second semiconductor substrate to add to a list of semiconductor substrates to be processed; and

assigning a first processing sequence to the first semiconductor substrate and a second processing sequence to the second semiconductor substrate.

5. The method of claim 4 , wherein generating the processing model for the batch of semiconductor substrates, comprises:

generating a processing model for the first semiconductor substrate and the second semiconductor substrate.

6. The method of claim 5 , further comprising:

identifying an additional semiconductor substrate in the batch to be processed;

upon identifying the additional semiconductor substrate, adding the additional semiconductor substrate to the list of substrates to be processed; and

generating a processing model for the list of semiconductor substrates to be processed.

7. The method of claim 1 , wherein generating a processing model for the batch of semiconductor substrates, comprises:

defining a sequence constraint for each processing chamber in the integrated substrate processing system.

8. A system, comprising:

a processor; and

a memory having instructions stored thereon, which, when executed by the processor, performs an operation for scheduling a semiconductor substrate processing sequence in an integrated substrate processing system, the operation comprising:

assigning a processing sequence to each semiconductor substrate in a batch of semiconductor substrates to be processed;

for each processing chamber in the integrated substrate processing system, assigning a processing chamber to each process in the processing sequence;

generating a processing model for the batch of semiconductor substrates, wherein the processing model defines a start time for each substrate in each processing chamber;

generating a timetable for the batch of semiconductor substrates based off the processing model; and

processing the batch of semiconductor substrates in accordance with the timetable.

9. The system of claim 8 , wherein the processing sequence is the same for each semiconductor substrate in the batch.

10. The system of claim 8 , wherein the processing sequence is not the same for each semiconductor substrate in the batch.

11. The system of claim 10 , wherein assigning the processing sequence to each semiconductor substrate in the batch of semiconductor substrates to be processed, comprises:

selecting a first semiconductor substrate and a second semiconductor substrate to add to a list of semiconductor substrates to be processed; and

assigning a first processing sequence to the first semiconductor substrate and a second processing sequence to the second semiconductor substrate.

12. The system of claim 11 , wherein generating the processing model for the batch of semiconductor substrates, comprises:

generating a processing model for the first semiconductor substrate and the second semiconductor substrate.

13. The system of claim 12 , further comprising:

identifying an additional semiconductor substrate in the batch to be processed;

upon identifying the additional semiconductor substrate, adding the additional semiconductor substrate to the list of substrates to be processed; and

generating a processing model for the list of semiconductor substrates to be processed.

14. The system of claim 8 , wherein generating a processing model for the batch of semiconductor substrates, comprises:

defining a sequence constraint for each processing chamber in the integrated substrate processing system.

15. A non-transitory computer readable medium having instructions stored thereon, which, when executed by a processor, cause the processor to perform a method of scheduling a semiconductor substrate processing sequence in an integrated substrate processing system, comprising:

assigning a processing sequence to each semiconductor substrate in a batch of semiconductor substrates to be processed;

for each processing chamber in the integrated substrate processing system, assigning a processing chamber to each process in the processing sequence;

generating a processing model for the batch of substrate, wherein the processing model define a start time for each substrate in each processing chamber;

generating a timetable for the batch of semiconductor substrates based off the processing model; and

processing the batch of semiconductor substrates in accordance with the timetable.

16. The non-transitory computer readable medium of claim 15 , wherein the processing sequence is the same for each semiconductor substrate in the batch.

17. The non-transitory computer readable medium of claim 15 , wherein the processing sequence is not the same for each semiconductor substrate in the batch.

18. The non-transitory computer readable medium of claim 17 , wherein assigning the processing sequence to each semiconductor substrate in the batch of semiconductor substrates to be processed, comprises:

selecting a first semiconductor substrate and a second semiconductor substrate to add to a list of semiconductor substrates to be processed; and

assigning a first processing sequence to the first semiconductor substrate and a second processing sequence to the second semiconductor substrate.

19. The non-transitory computer readable medium of claim 18 , wherein generating the processing model for the batch of semiconductor substrates, comprises:

generating a processing model for the first semiconductor substrate and the second semiconductor substrate.

20. The non-transitory computer readable medium of claim 19 , further comprising:

identifying an additional semiconductor substrate in the batch to be processed;

upon identifying the additional semiconductor substrate, adding the additional semiconductor substrate to the list of substrates to be processed; and

generating a processing model for the list of semiconductor substrates to be processed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2017
From: EMANI, SHYAM SUNDER
To: APPLIED MATERIALS, INC.
Reel/Frame 043709/0448 →
Continuity (1)
Related Publication 20190086906A1 · Mar 21, 2019
Cited By (2)
US 12,282,315 US 12,476,123