Electrostatic discharge protection device
An ESD protection device includes a semiconductor substrate of p-type conductivity, an epitaxial layer of p-type conductivity, a buried layer of n-type conductivity, device isolation layers, a first well of n-type conductivity, an emitter formed by implanting p-type impurities into an upper portion of the first well, a second well of p-type conductivity, a collector formed by implanting p-type impurities into an upper portion of the second well, a first P-body region interposed between the second well and the collector, a third well of n-type conductivity, a base formed by implanting n-type impurities into an upper surface portion of the third well, and a first deep well of n-type conductivity, interposed between the third well and the buried layer.
1. An electrostatic discharge (ESD) protection device comprising:
a semiconductor substrate of p-type conductivity;
an epitaxial layer of p-type conductivity, arranged over the semiconductor substrate;
a buried layer of n-type conductivity, interposed along a boundary between an upper surface of the semiconductor substrate and a lower surface of the epitaxial layer, the buried layer having a predetermined width;
a plurality of device isolation layers arranged within an upper portion of the epitaxial layer, having a predetermined depth and dividing the upper portion of the epitaxial layer into an emitter region, a collector region and a base region;
a first well of n-type conductivity, arranged in the emitter region of the epitaxial layer and having a first depth larger than that of the device isolation layers;
an emitter formed by implanting p-type impurities into an upper portion of the first well;
a second well of p-type conductivity, arranged in the collector region of the epitaxial layer and having a second depth larger than that of the device isolation layers;
a collector formed by implanting p-type impurities into an upper portion of the second well;
a first P-body region interposed between the second well and the collector;
a third well of n-type conductivity, formed in the base region of the epitaxial layer and having a third depth larger than that of the device isolation layers;
a base formed by implanting n-type impurities into an upper portion of the third well; and
a first deep well of n-type conductivity, interposed between the third well and the buried layer.
2. The ESD protection device of claim 1 , wherein the collector region is arranged between the emitter region and the base region; and the collector region and the base region are symmetrically arranged about the emitter region.
3. The ESD protection device of claim 1 , wherein the base region comprises a ring shape to surround the emitter region and the collector region.
4. The ESD protection device of claim 1 , further comprising a second deep well of n-type conductivity, interposed between the first well and the buried layer.
5. The ESD protection device of claim 1 , further comprising a second P-body region interposed between the first well and the emitter.
6. The ESD protection device of claim 1 , further comprising:
a second deep well of n-type conductivity, interposed between the first well and the buried layer; and
a second P-body region interposed between the first well and the emitter.
7. The ESD protection device of claim 1 , wherein the epitaxial layer further comprises a P-sub region, separated from the base region by one or more additional device isolation layers; and wherein the ESD protection device further comprises:
a fourth well of p-type conductivity, formed in the epitaxial layer of the P-sub region and having a fourth depth larger than that of the device isolation layers; and
a P-sub formed by implanting p-type impurities into an upper portion of the fourth well.
8. An electrostatic discharge (ESD) protection device comprising:
a semiconductor substrate of p-type conductivity;
an epitaxial layer of p-type conductivity, arranged over the semiconductor substrate;
a buried layer of n-type conductivity, interposed along a boundary between an upper surface of the semiconductor substrate and a lower surface of the epitaxial layer, the buried layer having a predetermined width;
a plurality of device isolation layers arranged within an upper portion of the epitaxial layer, having a predetermined depth and dividing the upper portion of the epitaxial layer into an emitter-collector region, and a base region;
at least two ion implantation blocking layers arranged on an upper surface of the epitaxial layer and dividing the emitter-collector region into an emitter region and a collector region;
a first well of n-type conductivity, arranged in the emitter region of the epitaxial layer and having a first depth larger than that of the device isolation layers;
an emitter formed by implanting p-type impurities into an upper portion of the first well;
a second well of p-type conductivity, formed in the collector region of the epitaxial layer and having a second depth larger than that of the device isolation layers;
a collector formed by implanting p-type impurities into an upper portion of the second well;
a first P-body region interposed between the second well and the collector;
a third well of n-type conductivity, formed in the base region of the epitaxial layer and having a third depth larger than that of the device isolation layers;
a base formed by implanting n-type impurities into an upper portion of the third well; and
a first deep well of n-type conductivity, interposed between the third well and the buried layer.
9. The ESD protection device of claim 8 , wherein the first well comprises a drift ion region of n-type conductivity.