System and method for controlling the impact of periodic jitter caused by non-ideal phase interpolators
In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.
1. A method for controlling periodic jitter arising from a phase interpolator (PI), comprising:
receiving incoming data;
receiving a reference clock of a fractional-N phase-locked loop (PLL), wherein N is an integer;
measuring a parts per million (PPM) offset between the incoming data and the reference clock, of a first PI; and
restricting jitter arising from the first PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the first PI, wherein the jitter arising from the first PI comprises jitter arising from non-linear phases of the first PI.
2. The method of claim 1 , further comprising reducing the PPM offset of the first PI to a target value or to be within a target value range.
3. The method of claim 1 , further comprising reducing the jitter arising from the first PI by reducing a frequency shift of the first PI or a frequency shift required by the first PI.
4. The method of claim 1 , further comprising reducing the jitter arising from the first PI by shifting a component of the jitter to reside outside of a predefined frequency range.
5. The method of claim 1 , further comprising performing clock and data recovery (CDR) using the incoming data and the reference clock.
6. The method of claim 1 , wherein receiving the incoming data comprises receiving the incoming data from a high speed serial communications link.
7. The method of claim 1 , wherein tuning a center frequency of the fractional-N PLL comprises adjusting the center frequency to or towards a desired frequency for transmitting outgoing data.
8. A method for controlling periodic jitter arising from a phase interpolator (PI), comprising:
receiving incoming data;
receiving a reference clock of a phase-locked loop (PLL);
measuring a parts per million (PPM) offset between the incoming data and the reference clock, of a first PI; and
restricting jitter arising from the first PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the PLL using a digital-analog converter (DAC) to reduce the PPM offset of the first PI, wherein the jitter arising from the first PI comprises jitter arising from non-linear phases of the first PI.
9. The method of claim 8 , further comprising reducing the PPM offset of the first PI to a target value or to be within a target value range.
10. The method of claim 8 , further comprising reducing the jitter arising from the first PI by reducing a frequency shift of the first PI or a frequency shift required by the first PI.
11. The method of claim 8 , further comprising reducing the jitter arising from the first PI by shifting a component of the jitter to reside outside of a predetermined frequency range.
12. The method of claim 8 , further comprising performing clock and data recovery (CDR) using the incoming data and the reference clock.
13. The method of claim 8 , wherein receiving the incoming data comprises receiving the incoming data from a high speed serial communications link.
14. The method of claim 8 , wherein restricting jitter arising from the first PI, to frequencies within a predefined bandwidth comprises setting a configuration of the DAC in a continuous mode.
15. A system for controlling periodic jitter arising from a phase interpolator (PI), comprising:
a receiver configured to receive incoming data;
a fractional-N phase-locked loop (PLL) configured to receive a reference clock, wherein N is an integer; and
measurement circuitry configured to measure a parts per million (PPM) offset between the incoming data and the reference clock, of a first PI,
wherein the fractional-N PLL is further configured to restrict jitter arising from the first PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the first PI, wherein the jitter arising from the first PI comprises jitter arising from non-linear phases of the first PI.
16. The system of claim 15 , wherein the fractional-N PLL is further configured to reduce the PPM offset of the first PI to a target value or to be within a target value range.
17. The system of claim 15 , wherein the fractional-N PLL is further configured to reduce the jitter arising from the first PI by reducing a frequency shift of the first PI or a frequency shift required by the first PI.
18. The system of claim 15 , wherein the fractional-N PLL is further configured to reduce the jitter arising from the first PI by shifting a component of the jitter to reside outside of a predetermined frequency range.
19. The system of claim 15 , wherein the receiver is further configured to receive the incoming data from a high speed serial communications link.
20. The system of claim 15 , wherein the fractional-N PLL is further configured to tune a center frequency of the fractional-N PLL by adjusting the center frequency to or towards a desired frequency for transmitting outgoing data.