Power supply wiring in a semiconductor memory device

1. A semiconductor device, comprising:

an uppermost metal layer including a power supply enhancing wiring;

power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer;

at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer; and

a memory bank, including:

a plurality of sense amplifiers;

a plurality of memory mats coupled to the sense amplifiers, the memory mats including first and second edge mats; and

a global input/output line coupled to the sense amplifiers and disposed over the first edge mat and not disposed over the second edge mat;

wherein the at least one memory device component disposed in vertical alignment with the via includes the second edge mat.

2. The semiconductor device of claim 1 , wherein the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer is a first via, the semiconductor device further comprising:

a column decoder adjacent to the second edge mat; and

a second via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the second via is disposed in vertical alignment with the column decoder.

3. The semiconductor device of claim 2 , further comprising:

a third via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the third via is disposed in vertical alignment with the second edge mat; and

a fourth via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the fourth via is disposed in vertical alignment with the column decoder.

4. The semiconductor device of claim 1 , wherein the memory bank is a first memory bank, the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer is a first via, and the global input/output line is a first global input/output line, the semiconductor device further comprising:

a second memory bank adjacent to the first memory bank, the second memory bank including:

a plurality of sense amplifiers;

a plurality of memory mats coupled to the sense amplifiers, the memory mats including a first and second edge mat; and

a second global input/output line coupled to the sense amplifiers of the second memory bank and disposed over the first edge mat of the second memory bank and not disposed over the second edge mat of the second memory bank;

a second via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the second via is disposed in vertical alignment with the second edge mat of the second memory bank.

5. The semiconductor device of claim 4 , further comprising:

a global bus line disposed over the first memory bank and not disposed over the second memory bank; and

a third via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the third via is disposed in vertical alignment with the second edge mat of the second memory bank and in horizontal alignment with the global bus line.

6. The semiconductor device of claim 5 , further comprising:

a fourth via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the fourth via is disposed in vertical alignment with the second edge mat of the first memory bank; and

a fifth via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the fifth via is disposed in vertical alignment with the second edge mat of the second memory bank.

7. The semiconductor device of claim 6 , further comprising:

a column decoder adjacent to the second edge mat of the first memory bank; and

a sixth via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the sixth via is disposed in vertical alignment with the column decoder; and

a seventh via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the seventh via is disposed in vertical alignment with the column decoder.

8. The semiconductor device of claim 7 , wherein the column decoder is a first column decoder, the semiconductor device further comprising:

a second column decoder adjacent to the second edge mat of the second memory bank;

an eighth via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the eight via is disposed in vertical alignment with the second column decoder; and

a ninth via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the ninth via is disposed in vertical alignment with the second column decoder.

9. A semiconductor device, comprising:

an uppermost metal layer including a power supply enhancing wiring;

power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer;

at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer;

a plurality of memory mats; and

a plurality of sense amplifiers arranged between at least some of the memory mats; wherein

the plurality of memory mats include first and second memory mats that are directly adjacent such that no sense amplifier of the plurality of sense amplifiers is disposed between the first and second memory mats; and

the at least one memory device component disposed in vertical alignment with the via includes the first memory mat.

10. The semiconductor device of claim 9 , wherein the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer is a second via, the semiconductor device further comprising:

a second via between the uppermost metal layer and the metal layer underlying the uppermost metal layer, wherein the second via is disposed in vertical alignment with the second edge mat.