Computational memory cell and processing array device using memory cells
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
1. A dual port static random access memory, comprising:
a memory cell having a storage cell, a read port for reading data from the storage cell and a write port for writing data to the storage cell;
an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell from a read bit line;
the read port having a read word line that is coupled to the isolation circuit and activates the isolation circuit and the read bit line that is coupled to the isolation circuit;
the write port having a write word line, a write bit line and complementary write bit line coupled to the memory cell;
the storage cell further comprising a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate of the first access transistor coupled to the write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate of the second access transistor coupled to the complementary write bit line;
wherein the write port further comprises a single write port transistor and the write word line coupled to a gate of the single write port transistor and wherein a drain of the single write port transistor is coupled to a source of the first access transistor and a source of the second access transistor; and
wherein the read bit line is capable of being used to provide read access to the storage cell data.
2. The memory of claim 1 , wherein the isolation circuit further comprises a first transistor whose gate is coupled to the read word line and a second transistor whose gate is coupled to the data signal.
3. The memory of claim 2 , wherein the isolation circuit first and second transistors are both NMOS transistors.
4. The memory of claim 2 , wherein the isolation circuit first and second transistors are both PMOS transistors.
5. The memory of claim 1 , wherein the data signal is one of a data signal and a complementary data signal.
6. The memory of claim 1 , wherein the write port further comprises a second write port transistor whose gate is coupled to write word line and whose drain is coupled to a source of the second access transistor.
7. The memory of claim 6 , wherein the isolation circuit further comprises a first transistor whose gate is coupled to the read word line and a second transistor whose gate is coupled to the data signal.
8. The memory of claim 7 , wherein the isolation circuit first and second transistors are both NMOS transistors.
9. The memory of claim 7 , wherein the isolation circuit first and second transistors are both PMOS transistors.
10. The memory of claim 6 , wherein the data signal is one of a data signal and a complementary data signal.
11. The memory of claim 6 , wherein the memory cell is capable of a selective write operation.
12. The memory of claim 6 , wherein the memory cell is capable of at least one of a boolean AND operation, a boolean NOR operation, a boolean NAND operation and a boolean OR operation.
13. The memory of claim 1 , wherein the memory cell is capable of a selective write operation.
14. The memory of claim 1 , wherein memory the cell is capable of at least one of a boolean AND operation, a boolean NOR operation, a boolean NAND operation and a boolean OR operation.
15. A dual port static random access memory, comprising:
a memory cell having a storage cell, a read port for reading data from the storage cell and a write port for writing data to the storage cell;
an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell from a read bit line wherein a gate of a first transistor of the isolation circuit is connected to the data signal;
the read port having a read word line that is coupled to the isolation circuit and activates the isolation circuit and the read bit line that is coupled to the isolation circuit;
the write port having a write word line, a write bit line and complementary write bit line coupled to the memory cell;
the storage cell further comprising a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate of the first access transistor being coupled to a write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate of the second access transistor being coupled to the complementary write bit line;
wherein the write port further comprises a single write port transistor and the write word line coupled to a gate of the single write port transistor and wherein a drain of the single write port transistor is coupled to a source of the first access transistor and a source of the second access transistor; and
wherein the read bit line is capable of being used to provide read access to the storage cell data.
16. The memory of claim 15 , wherein the isolation circuit further comprises a second transistor whose gate is coupled to the read word line and whose drain is connected to the read bit line.
17. The memory of claim 16 , wherein the isolation circuit first and second transistors are both NMOS transistors.
18. The memory of claim 16 , wherein the isolation circuit first and second transistors are both PMOS transistors.
19. The memory of claim 15 , wherein the data signal is one of a data signal and a complementary data signal.
20. The memory of claim 15 , wherein the write port further comprises a second write port transistor whose gate is coupled to a write bit line and whose drain is coupled to a source of the second access transistor.
21. The memory of claim 20 , wherein the isolation circuit further comprises a second transistor whose gate is coupled to the read word line and whose drain is connected to the read bit line.
22. The memory of claim 21 , wherein the isolation circuit first and second transistors are both NMOS transistors.
23. The memory of claim 21 , wherein the isolation circuit first and second transistors are both PMOS transistors.
24. The memory of claim 20 , wherein the data signal is one of a data signal and a complementary data signal.
25. The memory of claim 20 , wherein the memory cell is capable of a selective write operation.
26. The memory of claim 20 , wherein the memory cell is capable of at least one of a boolean AND operation, a boolean NOR operation, a boolean NAND operation and a boolean OR operation.
27. The memory of claim 15 , wherein the memory cell is capable of a selective write operation.
28. The memory of claim 15 , wherein the memory cell is capable of at least one of a boolean AND operation, a boolean NOR operation, a boolean NAND operation and a boolean OR operation.