IP Library Granted Patent US 10,032,630
Granted Patent B1
US 10,032,630 · App. 15/710,414 · Granted Jul 24, 2018

Method of manufacturing semiconductor device

Inventors: Katsuhiko Yamamoto (Toyama, JP); Hajime Karasawa (Toyama, JP); Kazuyuki Toyoda (Toyama, JP)
Assignee: HITACHI KOKUSAI ELECTRIC INC.
H01L21/0274G03F7/0002H01L21/3065H01L21/31133
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Quick Facts
Patent No.
US 10,032,630
App. No.
15/710,414
Granted
Jul 24, 2018
Kind
B1
Abstract

There is provided a technique for facilitating a patterning process by the DSA appropriately and efficiently. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including (a) accommodating in a process chamber a substrate having a guide pattern thereon; (b) supplying a plasma of a first process gas into the process chamber to subject the substrate to first one of a first process for hydrophilizing the substrate and a second process for hydrophobilizing the substrate; and (c) supplying a plasma of a second process gas into the process chamber to subject the substrate to second one of the first process and the second process other than the first one of the first process and the second process.

Claims (14)

1. A method of manufacturing a semiconductor device, comprising: (a) accommodating iii a process chamber a substrate having a guide pattern thereon; (b) supplying a plasma of a first process gas into the process chamber to subject the substrate to first one of a first process for hydrophilizing the substrate and a second process for hydrophobilizing the substrate: and (c) supplying a plasma of a second process gas into the process chamber to subject the substrate to second one of the first process and the second process other than the first one of the first process and the second process; wherein the first process gas and the second process gas comprise a hydrogen-containing gas and a fluorine-containing gas, respectively, when the first process the second process are performed in (b) and (c), respectively, and the first process gas and the second process gas comprise a fluorine-containing gas and a hydrogen-containing gas, respectively, when the second process and the first process are performed in (b) and (c), respectively.

2. The method of claim 1 , wherein (b) is performed without a bias applied to the substrate, and (c) is performed with a bias applied to the substrate.

3. The method of claim 2 , wherein an inner pressure of the process chamber in (c) is lower than that of the process chamber in (b).

4. The method of claim 3 , further comprising: (d) supplying a purge gas into the process chamber between (b) and (c).

5. The method of claim 3 , wherein the first process is performed isotropically, and the second process is performed anisotropically.

6. The method of claim 5 , further comprising: (e) applying a self-assembly photoresist material containing a combination of two polymers having different molecular weights on the substrate.

7. The method of claim 2 , further comprising: (d) supplying a purge gas into the process chamber between (b) and (c).

8. The method of claim 2 , wherein the first process is performed isotropically, and the second process is performed anisotropically.

9. The method of claim 1 , wherein an inner pressure of the process chamber in (c) is lower than that of the process chamber in (b).

10. The method of claim 1 , further comprising: (d) supplying a purge gas into the process chamber between (b) and (c).

11. The method of claim 1 , wherein the first process is performed isotropically, and the second process is performed anisotropically.

12. The method of claim 1 , further comprising: (e) applying a self-assembly photoresist material containing a combination of two polymers having different molecular weights on the substrate.

13. The method of claim 1 , wherein a wettability of an exposed surface of the substrate differs from that of a side surface of the guide pattern after (c) is performed.

14. The method of claim 1 , further comprising: (e) applying a photoresist material containing two or more organic materials on an exposed surface of the substrate where the guide pattern is not formed.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2018
From: HITACHI KOKUSAI ELECTRIC INC.
To: KOKUSAI ELECTRIC CORPORATION
Reel/Frame 047995/0490 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2017
From: YAMAMOTO, KATSUHIKO; KARASAWA, HAJIME; TOYODA, KAZUYUKI
To: HITACHI KOKUSAI ELECTRIC INC.
Reel/Frame 043642/0697 →
Priority Claims (1)
JP 2017-049002 · Mar 14, 2017 · national