Methods used in forming an array of elevationally-extending transistors

1. A method used in forming an array of elevationally-extending transistors, comprising:

forming vertically-alternating tiers of insulating material and void space;

forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers;

filling the void-space tiers with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers; and

after the filling, forming transistor channel material in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.

2. The method of claim 1 wherein the flowing is through (a): the individual longitudinally-aligned channel openings that extend elevationally through the insulating-material tiers.

3. The method of claim 1 wherein the flowing is only through (a): the individual longitudinally-aligned channel openings that extend elevationally through the insulating-material tiers, and the flowing is not through (b): the horizontally-elongated trenches that extend elevationally through the insulating-material tiers.

4. The method of claim 3 comprising both forming (b): the horizontally-elongated trenches that extend elevationally through the insulating-material tiers and forming solid material within said trenches after the flowing through (a).

5. The method of claim 3 comprising both forming (b): the horizontally-elongated trenches that extend elevationally through the insulating-material tiers and forming solid material within said trenches before the flowing through (a).

6. The method of claim 1 comprising:

forming elevationally-extending through-array-via openings through the insulating-material tiers before forming the void-space tiers; and

forming an electrically-operative through-array via in individual of the through-array-via openings which remains in a finished construction of the array.

7. The method of claim 1 wherein each of the trenches and the channel openings are formed to be vertical or within 10° of vertical.

8. The method of claim 1 wherein the flowing is through (b): the horizontally-elongated trenches that extend elevationally through the insulating-material tiers.

9. The method of claim 1 wherein the flowing is through (a): the individual longitudinally-aligned channel openings that extend elevationally through the insulating-material tiers and the flowing is through (b): the horizontally-elongated trenches that extend elevationally through the insulating-material tiers.

10. The method of claim 1 wherein the flowing is only through (b): the horizontally-elongated trenches that extend elevationally through the insulating-material tiers, and the flowing is not through (a): the individual longitudinally-aligned channel openings that extend elevationally through the insulating-material tiers.

11. The method of claim 10 comprising both forming (a): the individual longitudinally-aligned channel openings that extend elevationally through the insulating-material tiers and forming solid material within said channel openings after the flowing through (b).

12. The method of claim 10 comprising both forming (a): the individual longitudinally-aligned channel openings that extend elevationally through the insulating-material tiers and forming solid material within said channel openings before the flowing through (b).

13. The method of claim 1 comprising forming the transistor channel material in the trenches while forming the transistor channel material in the individual channel openings and which remains in the trenches in a finished construction of the array.

14. The method of claim 1 comprising:

forming elevationally-extending dummy-structure openings through the insulating-material tiers before forming the void-space tiers;

forming the trenches before forming the void-space tiers; and

forming the transistor channel material in the dummy-structure openings and in the trenches while forming the transistor channel material in the individual channel openings and which remains in the dummy-structure openings and in the trenches in a finished construction of the array.

15. The method of claim 1 comprising forming charge- passage material in the individual channel openings along the insulating- material tiers and along the conductive material in the filled void-space tiers before forming the transistor channel material.

16. The method of claim 15 comprising forming the transistor channel material directly along the charge-passage material.

17. The method of claim 15 comprising forming a charge-blocking material and at least one of a charge-storage material or a charge-trapping material along the insulating-material tiers and along the conductive material in the filled void-space tiers before forming the charge- passage material.

18. A method used in forming an array of elevationally-extending transistors, comprising:

forming vertically-alternating tiers of insulating material and void space, individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers;

filling the void-space tiers with conductive material by flowing the conductive material or one or more precursors thereof through the channel openings to into the void-space tiers, the filling forming the conductive material elevationally along the insulating-material tiers within individual of the channel openings;

after the filling, removing the conductive material from being elevationally along the insulating-material tiers within the individual channel openings; and

forming transistor channel material in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers after the removing.

19. The method of claim 18 comprising forming horizontally-elongated trenches extending elevationally through the insulating-material tiers and forming solid material within said trenches.

20. The method of claim 19 comprising forming elevationally-extending dummy structures through the insulating-material tiers that are laterally between the trenches and solid material therein in a finished construction of the array.

21. The method of claim 19 comprising forming electrically-operative elevationally-extending through-array vias through the insulating-material tiers that are laterally between the trenches and solid material therein in a finished construction of the array.

22. The method of claim 19 wherein the trenches and the solid material therein are formed after forming the individual channel openings.

23. The method of claim 19 wherein the trenches and the solid material therein are formed before forming the individual channel openings.

24. The method of claim 23 wherein the solid material comprises the transistor channel material.

25. A method used in forming an array of elevationally-extending transistors, comprising:

forming vertically-alternating tiers of different composition first and second materials, the first material being insulative;

forming elevationally-extending dummy structures through the vertically-alternating tiers;

forming elevationally-extending channel openings into the vertically-alternating tiers after forming the dummy structures;

flowing an etchant into the channel openings and etching therewith at least some of the second material of the second-material tiers selectively relative to the first-material tiers and selectively relative to the dummy structures to form void space elevationally between immediately-adjacent of the first-material tiers;

filling the void space with conductive material by flowing the conductive material or one or more precursors thereof through the channel openings to into the void space, the filling forming the conductive material elevationally along the first-material tiers within individual of the channel openings;

after filling the void space, removing the conductive material from being elevationally along the first-material tiers within the individual channel openings;

forming transistor channel material in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void space after the removing;

forming horizontally-elongated trenches extending elevationally through the first-material tiers; and

forming solid material within said trenches.

26. The method of claim 25 wherein ratio of a total number of the channel openings to a total number of the dummy structures is from 20:1 to 4:1.

27. The method of claim 25 wherein the trenches and solid material therein are formed before forming the channel openings and transistor channel material therein.

28. The method of claim 25 wherein the trenches and solid material therein are formed after forming the channel openings and transistor channel material therein.

29. The method of claim 25 comprising:

forming horizontally-elongated trenches extending elevationally through the first-material tiers; and

forming solid material within said trenches.