Manufacturing method of interconnect structure

1. A manufacturing method of an interconnect structure, comprising:

forming a dielectric layer on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer;

forming a metal layer on a surface of the opening, wherein the metal layer is in direct contact with the silicon layer;

forming a stress adjustment layer on the metal layer;

performing a thermal process to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer;

removing the stress adjustment layer after the thermal process is performed; and

forming a barrier layer on the surface of the opening, wherein a compressive stress of the stress adjustment layer is greater than a compressive stress of the barrier layer.

2. The manufacturing method of the interconnect structure of claim 1 , wherein the stress adjustment layer and the barrier layer are formed by using different deposition methods.

3. The manufacturing method of the interconnect structure of claim 1 , wherein the silicon layer comprises a silicon substrate or an epitaxial silicon layer.

4. The manufacturing method of the interconnect structure of claim 1 , wherein a forming method of the dielectric layer comprises a chemical vapor deposition method.

5. The manufacturing method of the interconnect structure of claim 1 , wherein a material of the metal layer comprises titanium, nickel, or cobalt.

6. The manufacturing method of the interconnect structure of claim 1 , wherein a forming method of the metal layer comprises a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method.

7. The manufacturing method of the interconnect structure of claim 1 , wherein a material of the stress adjustment layer comprises titanium nitride, silicon nitride, or a combination thereof.

8. The manufacturing method of the interconnect structure of claim 1 , wherein a forming method of the stress adjustment layer comprises a radio frequency physical vapor deposition (RF-PVD) method.

9. The manufacturing method of the interconnect structure of claim 1 , wherein a stress of the stress adjustment layer is adjusted by configuring a variable capacitance of a deposition machine.

10. The manufacturing method of the interconnect structure of claim 1 , wherein the stress adjustment layer further completely fills the opening.

11. The manufacturing method of the interconnect structure of claim 1 , wherein the thermal process comprises an annealing process.

12. The manufacturing method of the interconnect structure of claim 1 , wherein a material of the metal silicide layer comprises titanium silicide, nickel silicide, or cobalt silicide.

13. The manufacturing method of the interconnect structure of claim 1 , further comprising removing the metal layer not reacted with the silicon layer at the same time of removing the stress adjustment layer.

14. The manufacturing method of the interconnect structure of claim 1 , wherein a removal method of the stress adjustment layer comprises a wet etching method.

15. The manufacturing method of the interconnect structure of claim 14 , wherein an etchant of the wet etching method comprises diluted hydrofluoric acid or a sulfuric peroxide mixture.

16. The manufacturing method of the interconnect structure of claim 1 , wherein a material of the barrier layer comprises titanium nitride.

17. The manufacturing method of the interconnect structure of claim 1 , wherein a forming method of the barrier layer comprises a CVD method or an atomic layer deposition (ALD) method.

18. The manufacturing method of the interconnect structure of claim 1 , further comprising forming a conductive layer completely filling the opening on the barrier layer.

19. The manufacturing method of the interconnect structure of claim 18 , wherein a material of the conductive layer comprises tungsten.

20. The manufacturing method of the interconnect structure of claim 18 , wherein a forming method of the conductive layer comprises a PVD method.