Semiconductor devices including support patterns
A semiconductor device includes a plurality of pillar structures on a semiconductor substrate, and a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another, wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including at least a first support hole and a second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other.
1. A semiconductor device, comprising:
a plurality of pillar structures on a semiconductor substrate, the semiconductor substrate including a cell region and a dummy region; and
a support pattern in contact with at least a part of each of the plurality of pillar structures, the support pattern connecting the plurality of pillar structures with one another,
wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including a plurality of first support holes and at least one second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other, and
wherein the plurality of the first support holes are on a central portion of the cell region, and the at least one second support hole is only at an edge portion of the cell region among the central and edge portions of the cell region.
2. The semiconductor device as claimed in claim 1 , wherein the support holes further include a third support hole having a shape different from those of the first and second support holes.
3. The semiconductor device as claimed in claim 1 , wherein each of the pillar structures has a circular cross-section in plan view, and the support holes have circular or polygonal cross-sections in plan view, a cross-section of each of the support holes being defined by connecting central points of the circular cross-sections of the pillar structures.
4. The semiconductor device as claimed in claim 1 , wherein the pillar structures are spaced apart from each other at a same interval, and six pillar structures surrounding each of the pillar structures constitute a honeycomb shape.
5. The semiconductor device as claimed in claim 1 , wherein:
the pillar structures include memory pillar structures on the cell region and dummy pillar structures on the dummy region, only the memory pillar structures of the pillar structures to perform a memory function, and
the support holes expose side surfaces of all of the memory pillar structures.
6. The semiconductor device as claimed in claim 5 , wherein the support holes are on the cell region.
7. The semiconductor device as claimed in claim 5 , wherein at least one of the dummy pillar structures is on the cell region and has a side surface exposed through the support holes.
8. The semiconductor device as claimed in claim 1 , wherein each of the support holes simultaneously exposes side surfaces of three to seven pillar structures.
9. The semiconductor device as claimed in claim 1 , wherein:
the plurality of first support holes have a same shape as each other, and
a total number of the plurality of first support holes is greater than that of the at least one second support hole.
10. The semiconductor device as claimed in claim 9 , wherein:
the first support holes have circular cross-sections in plan view, a perimeter of each circular cross-section extending through central points of cross-sections of pillar structures exposed through the first support holes in plan view, and
the at least one second support hole has a polygonal cross-sections in plan view, a perimeter of the polygonal cross-section extending through central points of cross-sections of pillar structures exposed through the at least one second support hole in plan view.
11. The semiconductor device as claimed in claim 1 , wherein each of the pillar structures is a bottom electrode and has a plug shape.
12. The semiconductor device as claimed in claim 1 , further comprising:
a dielectric layer conformally covering a surface of the support pattern and surfaces of the pillar structures; and
a top electrode on the dielectric layer.
13. A semiconductor device, comprising:
a plurality of pillar structures on a semiconductor substrate, the semiconductor substrate including a cell region and a dummy region; and
a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another,
wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including a plurality of first support holes and at least one second support hole that are spaced apart from each other,
wherein the plurality of first support holes have a different shape from that of the at least one second support hole,
wherein the pillar structures include memory pillar structures on the cell region and dummy pillar structures on the dummy region, only the memory pillar structures of the pillar structures to perform a memory function, and
wherein the support holes are on the cell region, the support holes exposing side surfaces of all of the memory pillar structures on the cell region.
14. The semiconductor device as claimed in claim 13 , wherein each of the support holes simultaneously exposes side surfaces of three to seven pillar structures.
15. The semiconductor device as claimed in claim 13 , wherein the pillar structures are spaced apart from each other at a same interval, six pillar structures surrounding each of the pillar structures constitute a honeycomb shape.
16. A semiconductor device, comprising:
a plurality of electrode pillars on a semiconductor substrate; and
a support pattern in contact with at least a part of each of the plurality of electrode pillars, the support pattern connecting the plurality of electrode pillars with one another,
wherein the support pattern includes support holes therethrough, the support holes including at least one first support hole and at least one second support hole that are spaced apart from each other, the at least one first support hole and the at least one second support hole having different shapes from each other in plan view, and
wherein the at least one first support hole is a plurality of first support holes, a total number of the plurality of first support holes being larger than that of the at least one second support hole.
17. The semiconductor device as claimed in claim 16 , wherein the semiconductor substrate includes a cell region and a dummy region, the support pattern overlapping the cell region and the dummy region, and the support holes overlapping only the cell region.
18. The semiconductor device as claimed in claim 17 , wherein the at least one second support hole is at an edge of the cell region.
19. The semiconductor device as claimed in claim 16 , wherein each one of the support holes partially overlaps at least three adjacent electrode pillars of the plurality of electrode pillars.