Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times
View Patent ↗Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
1. An apparatus, comprising:
a clock generator circuit comprising a two-phase flip-flop circuit configured to provide an output signal, wherein the two-phase flip-flop circuit comprises a two-phase flip-flop and a driver circuit, wherein the two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal, wherein the first driver control signal and the second driver control signal are complementary, wherein the driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal, wherein the two-phase flip-flop comprises:
a master latch configured to receive an input signal and to latch a first signal at a first node in response to the clock signal and latch a second signal at a second node in response to the clock signal, wherein the master latch comprises a clocked inverter coupled to a NAND gate, wherein the clocked inverter is configured to provide the input signal to the NAND gate responsive to the clock signal; wherein the NAND gate is configured to receive a reset signal and is configured to provide an output to the first node responsive to the reset signal and the output of the inverter;
a first slave latch configured to latch the first signal at a third node in response to the clock signal, wherein the first driver control signal is provided from the third node; and
a second slave latch configured to latch the second signal at a fourth node in response to the clock signal, wherein the second driver control signal is provided from the fourth node.
2. The apparatus of claim 1 , wherein the first node of the master latch is coupled to the second node of the master latch via an inverter.
3. The apparatus of claim 1 , wherein the first slave latch comprises a first passgate configured to pass the first signal to the third node responsive to the clock signal, and wherein the second slave latch comprises a second passgate configured to pass the second signal to the fourth node responsive to the clock signal.
4. The apparatus of claim 1 , wherein the clock generator circuit further comprises a phase splitter configured to provide the clock signal and a complementary clock signal responsive to an input clock signal.
5. The apparatus of claim 1 , wherein the clock generator circuit further comprises a series of inverters configured to drive the output signal to downstream circuitry.
6. The apparatus of claim 1 , wherein the output signal is a first output signal, wherein the driver circuit is further configured to provide a second output signal responsive to the first driver control signal and the second driver control signal, wherein the second output signal is complementary to the first output signal.
7. The apparatus of claim 1 , wherein the driver circuit comprises a pull-up circuit configured to drive the output signal to logical high value responsive to the clock signal and pull-down circuit configured to drive the output signal to logical low value responsive to the clock signal.
8. The apparatus of claim 7 , wherein the pull-up circuit includes a passgate that is symmetrical with a passgate of the pull-down circuit.