Nonvolatile memory device
A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
1. A nonvolatile memory device comprising:
a memory cell array including a plurality of planes;
a plurality of page buffers arranged corresponding to each of the plurality of planes; and
a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers, wherein
each of the plurality of page buffers comprises a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal, and
the control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
2. The nonvolatile memory device of claim 1 , wherein each of the plurality of page buffers comprises a first page buffer and a second page buffer,
wherein a plurality of bit lines included in the plurality of planes are configured to form a first bit line group and a second bit line group, and
wherein the first page buffer is connected to a single bit line of the first bit line group and a single bit line of the second bit line group, and the second page buffer is connected to another bit line of the first bit line group and another bit line of the second bit line group.
3. The nonvolatile memory device of claim 1 , wherein the control logic circuit is configured to delay the transition time of the bit line setup signal according to a transmission distance by which the bit line shutoff signal is transmitted to a page buffer from among the plurality of page buffers, and to increase the delay as the transmission distance is increased.
4. The nonvolatile memory device of claim 3 , wherein the control logic circuit is configured to store information corresponding to a set transition time of each of the plurality of planes based on the transmission distance, and to transmit the bit line setup signal to the plurality of page buffers based on the information.
5. The nonvolatile memory device of claim 1 , wherein the control logic circuit is configured to simultaneously perform a read operation on at least some of the plurality of planes.
6. The nonvolatile memory device of claim 5 , wherein as a number of the at least some of the plurality of planes increases, the control logic circuit is configured to delay the transition time.
7. The nonvolatile memory device of claim 6 , wherein the control logic circuit is configured to store information corresponding to set transition times for various numbers of the plurality of planes available for the read operation, and to transmit the bit line setup signal to page buffers connected to the at least some of the plurality of planes based on the information.
8. The nonvolatile memory device of claim 1 , wherein the transition time is a point in time when a level of the bit line shutoff signal reaches the second level.
9. The nonvolatile memory device of claim 1 , wherein the control logic circuit is configured to adjust the transition time based on a difference value between the first level and the second level of the bit line shutoff signal.
10. The nonvolatile memory device of claim 1 , wherein the shutoff circuit comprises a transistor, and the transistor is turned on and off according to the bit line shutoff signal.
11. A nonvolatile memory device comprising:
a memory cell array including a plurality of planes;
a plurality of page buffers connected to each of the plurality of planes; and
a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers, wherein
each of the plurality of page buffers comprises a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal, and
the control logic circuit is configured to change a level of the bit line setup signal based on a result of comparing a level of the bit line shutoff signal with a level of a reference voltage.
12. The nonvolatile memory device of claim 11 , wherein the level of the reference voltage is determined based on a sensing margin for sensing on-cells and off-cells of each of the plurality of page buffers connected to each of the plurality of planes.
13. The nonvolatile memory device of claim 11 , wherein according to the comparing of the level of the bit line shutoff signal with the level of the reference voltage by the control logic circuit, a point in time when the level of the bit line setup signal is changed is controlled according to a number of planes simultaneously selected for a read operation.
14. The nonvolatile memory device of claim 11 , wherein according to the comparing of the level of the bit line shutoff signal with the level of the reference voltage by the control logic circuit, a point in time when the level of the bit line setup signal is changed is controlled according to a distance by which the bit line shutoff signal is transmitted to each of the plurality of page buffers.
15. The nonvolatile memory device of claim 11 , wherein the control logic circuit is configured to control the plurality of page buffers to simultaneously develop the bit line and the sensing node.
16. A nonvolatile memory device comprising:
a memory cell array including a plurality of planes;
a plurality of page buffers arranged as respectively corresponding to the plurality of planes,
wherein each of the plurality of page buffers is configured to precharge a sensing node and a bit line in a corresponding plane of the plurality planes responsive to a bit line setup signal, and to perform a shutoff operation responsive to a bit line shutoff signal; and
a control logic circuit configured to generate the bit line setup signal as having a level that is changed at a transition time controlled according to a gradient of the bit line shutoff signal.
17. The nonvolatile memory device of claim 16 , wherein the control logic circuit is configured to delay the transition time of the bit line setup signal from a point in time when the bit line shutoff signal starts to decrease from a first level to a second level.
18. The nonvolatile memory device of claim 17 , wherein the control logic circuit is configured to simultaneously perform a read operation on at least some of the plurality of planes, and to determine the delay according to a number of the plurality of planes on which the read operation is simultaneously performed.
19. The nonvolatile memory device of claim 17 , wherein the control logic circuit is configured to determine the delay according to a transmission distance by which the bit line shutoff signal is transmitted to a page buffer from among the plurality of page buffers during a read operation.
20. The nonvolatile memory device of claim 16 , wherein the control logic circuit is configured to change the level of the bit line setup signal based on a result of comparing the level of the bit line shutoff signal with a level of a reference voltage.