Controller area network frame override

1. A method to suppress malicious transmissions by overriding frames on a Controller Area Network (CAN) bus, comprising:

determining when a frame arrives at a CAN bus;

receiving, from the CAN bus, an arbitration identification (ID) of the frame;

determining whether to override the frame based on the arbitration ID;

in response to determining to override the frame, transmitting a predetermined sequence of bits on the CAN bus during transmission of a data length code (DLC) field of the frame to override the frame without triggering an error on the CAN bus;

generating a message that completes and validates the overridden frame based on the predetermined sequence of bits; and

transmitting the message on the CAN bus to complete transmission of the overridden frame.

2. The method of claim 1 , wherein the predetermined sequence of bits comprises a predetermined number of consecutive dominant bits.

3. The method of claim 1 , wherein determining whether to override the frame comprises:

determining whether to override the frame before receiving a cyclic redundancy check (CRC) of the frame.

4. The method of claim 1 , wherein determining whether to override the frame comprises:

determining whether a plurality of IDs comprises the arbitration ID.

5. The method of claim 4 , wherein determining whether to override the frame comprises:

receiving a plurality of statuses of a vehicle; and

determining whether to override the frame based on whether the plurality of statuses matches a plurality of criteria.

6. The method of claim 1 , wherein generating the message comprises:

calculating a CRC that validates the frame, and wherein the message includes the CRC.

7. The method of claim 1 , wherein transmitting the predetermined sequence of bits on the CAN bus comprises:

tracking a field of the frame to be transmitted on the CAN bus; and

determining that the field is the DLC field.

8. The method of claim 1 , wherein transmitting the predetermined sequence of bits comprises:

retrieving the predetermined sequence of bits from a memory.

9. The method of claim 8 , comprising:

receiving a DLC of a second frame related to the frame before receiving the frame;

in response to determining to override the second frame, determining whether the DLC includes a recessive bit;

in response to determining that the DLC includes the recessive bit, generating a new DLC having the recessive bit flipped to a dominant bit; and

storing the new DLC in the memory.

10. The method of claim 1 , wherein generating the message comprises:

retrieving a pre-stored message associated with the arbitration ID and the predetermined sequence of bits.

11. A system to suppress malicious transmissions by overriding frames on a Controller Area Network (CAN) bus, comprising:

one or more integrated circuits configured to:

determine when a frame arrives at a CAN bus;

receive, from the CAN bus, an arbitration identification (ID) of the frame;

determine whether to override the frame based on the arbitration ID;

in response to determining to override the frame, transmitting a predetermined sequence of bits on the CAN bus during transmission of a data length code (DLC) field of the frame to override the frame without triggering an error on the CAN bus;

generate a message that completes and validates the overridden frame based on the predetermined sequence of; and

transmit the message on the CAN bus to complete transmission of the overridden frame.

12. The system of claim 11 , wherein the predetermined sequence of bits comprises a predetermined number of consecutive dominant bits.

13. The system of claim 11 , wherein to determine whether to override the frame, the one or more integrated circuits are configured to:

determine whether to override the frame before receiving a cyclic redundancy check (CRC) of the frame.

14. The system of claim 11 , wherein to determine whether to override the frame, the one or more integrated circuits are configured to:

determine whether a plurality of IDs comprises the arbitration ID.

15. The system of claim 14 , wherein to determine whether to override the frame, the one or more integrated circuits are configured to:

receive a plurality of statuses of a vehicle; and

determine whether to override the frame based on whether the plurality of statuses matches a plurality of criteria.

16. The system of claim 11 , wherein to generate the message, the one or more integrated circuits are configured to:

calculate a cyclic redundancy check (CRC) that validates the frame, and wherein the message includes the CRC.

17. The system of claim 11 , wherein to transmit the predetermined value on the CAN bus, the one or more integrated circuits are configured to:

track a field of the frame to be transmitted on the CAN bus; and

determine that the field is the DLC field.

18. The system of claim 11 , wherein to transmit the predetermined value, the one or more integrated circuits are configured to:

retrieve the predetermined sequence of bits from a memory.

19. The system of claim 18 , wherein the one or more integrated circuits are configured to:

receive a DLC of a second frame related to the frame before receiving the frame;

in response to determining to override the second frame, determine whether the DLC includes a recessive bit;

in response to determining that the DLC includes the recessive bit, generate a new DLC having the recessive bit flipped to a dominant bit; and

store the new DLC in the memory.

20. The system of claim 11 , wherein the system is implemented in an Electronic Control Unit (ECU) coupled to the CAN bus.

21. The system of claim 11 , wherein the one or more integrated circuits comprise a field-programmable gate array (FPGA).