Memory system with on-the-fly error detection and termination and operating method thereof
Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.
1. A decoding method, comprising:
calculating cyclic redundancy check (CRC) parity bits for data on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data; and
terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.
2. The method of claim 1 , further comprising determining LDPC checksum in accordance with the LDPC decoding.
3. The method of claim 2 , wherein the terminating of the LDPC decoding comprises terminating the LDPC decoding when the generated CRC parity bits match with the CRC bits in the data and it is determined that the LDPC checksum is less than a predetermined threshold.
4. The method of claim 3 , wherein the terminating of the LDPC decoding further comprises outputting hard decision values in accordance with the LDPC decoding.
5. The method of claim 1 , wherein the updating of the calculated CRC parity bits comprises updating the calculated CRC parity bits by feeding predetermined bits into a CRC encoder.
6. The method of claim 1 , wherein the performing of the LDPC decoding for the data comprises processing, for each iteration of the LDPC decoding, updating messages for a circulant.
7. A memory system, comprising:
a storage; and
a decoder coupled to the storage and suitable for:
calculating cyclic redundancy check (CRC) parity bits for data from the storage on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data; and
terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.
8. The memory system of claim 7 , wherein the decoder is further suitable for determining LDPC checksum in accordance with the LDPC decoding.
9. The memory system of claim 8 , wherein the decoder is further suitable for terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match with the CRC bits and it is determined that the LDPC checksum is less than a predetermined threshold.
10. The memory system of claim 9 , wherein the decoder is further suitable for outputting hard decision values in accordance with the LDPC decoding.
11. The memory system of claim 7 , wherein the decoder is further suitable for updating the calculated CRC parity bits by feeding predetermined bits into a CRC encoder.
12. The memory system of claim 7 , wherein the decoder is further suitable for performing of the LDPC decoding for the data by processing, for each iteration of the LDPC decoding, updating messages for a circulant.
13. A memory controller, comprising:
a receiver suitable for receiving data; and
a decoder coupled with the receiver and suitable for:
calculating cyclic redundancy check (CRC) parity bits for data on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data; and
terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.
14. The memory controller of claim 13 , wherein the decoder is further suitable for determining LDPC checksum in accordance with the LDPC decoding.
15. The memory controller of claim 14 , wherein the decoder is further suitable for terminating the LDPC decoding, when the comparing indicates that the generated CRC parity bits match with the CRC bits and it is determined that the LDPC checksum is less than a predetermined threshold.
16. The memory controller of claim 15 , wherein the decoder is further suitable for outputting hard decision values in accordance with the LDPC decoding.
17. The memory controller of claim 13 , wherein the decoder is further suitable for updating the calculated CRC parity bits by feeding predetermined bits into a CRC encoder.
18. The memory controller of claim 13 , wherein the decoder is further suitable for performing of the LDPC decoding for the data by processing, for each iteration of the LDPC decoding, updating messages for a circulant.