Apparatuses and methods for a memory device with dual common data I/O lines
View Patent ↗Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
1. An apparatus comprising:
a bit line pair;
a sense amplifier coupled to the bit line pair;
a first I/O line pair;
a second I/O line pair;
a first transfer gate coupled between the sense amplifier and the first I/O line pair; and
a second transfer gate coupled between the sense amplifier and the second I/O line pair.
2. The apparatus of claim 1 , further comprising:
a first decoder coupled to the first transfer gate and configured to receive an address decoded signal; and
a second decoder coupled to the second transfer gate and configured to receive the address decoded signal.
3. The apparatus of claim 2 , further comprising:
a first main amplifier coupled to the first I/O line pair; and
a second main amplifier coupled to the second I/O line pair.
4. The apparatus of claim 3 , further comprising a multiplexer configured to couple at least one of output nodes of the first main amplifier and the second amplifier to an output node of the multiplexer.
5. The apparatus of claim 4 , further comprising a control circuit configured to:
alternately provide a control signal to the first decoder and the second decoder to activate at least one of the first decoder and the second decoder which receives the control signal; and
provide the control signal to the multiplexer to select the at least one of the output nodes of the first main amplifier and the second main amplifier.
6. The apparatus of claim 2 , further comprising a control circuit configured to alternately provide a control signal to the first decoder and the second decoder to activate one of the first decoder and the second decoder which receives the control signal.
7. The apparatus of claim 1 , further comprising:
an additional bit line pair;
an additional sense amplifier coupled to the additional bit line pair;
a third transfer gate coupled between the additional sense amplifier and the first I/O line pair; and
a fourth transfer gate coupled between the additional sense amplifier and the second I/O line pair.
8. The apparatus of claim 7 , further comprising:
a third decoder coupled to the third transfer gate and configured to receive an additional address decoded signal; and
a fourth decoder coupled to the fourth transfer gate and configured to receive the additional address decoded signal.
9. The apparatus of claim 8 , further comprising:
a first main amplifier coupled to the first I/O line pair; and
a second main amplifier coupled to the second I/O line pair.
10. The apparatus of claim 9 , further comprising a multiplexer configured to couple at least one of output nodes of the first main amplifier and the second amplifier to an output node of the multiplexer.
11. The apparatus of claim 10 , further comprising a control circuit configured to:
alternately provide a control signal to each of the first and third decoders and each of the second and fourth decoders to activate one of each of the first and third decoders and each of the second and fourth decoders which receives the control signal; and
provide the control signal to the multiplexer to select the at least one of the output nodes of the first main amplifier and the second main amplifier.
12. The apparatus of claim 8 , further comprising a control circuit configured to alternately provide a control signal to each of the first and third decoders and each of the second and fourth decoders to activate one of each of the first and third decoders and each of the second and fourth decoders which receives the control signal.
13. An apparatus comprising:
a first sense amplifier;
a second sense amplifier;
a first I/O line pair;
a second I/O line pair;
a first transfer gate coupled between the first sense amplifier and the first I/O line pair;
a second transfer gate coupled between the second sense amplifier and the second I/O line pair;
a first main amplifier coupled to the first I/O line pair; and
a second main amplifier coupled to the second I/O line pair,
wherein the first transfer gate is conductive and the first main amplifier is activated when the second transfer gate is nonconductive and the second main amplifier is inactivated.
14. The apparatus of claim 13 , wherein the second transfer gate is conductive and the second main amplifier is activated when the first transfer gate is nonconductive and the first main amplifier is inactivated.
15. The apparatus of claim 14 , further comprising a multiplexer coupled to the first main amplifier and the second main amplifier, the multiplexer configured to select at least one of a first output of the first main amplifier and a second output of the second main amplifier.
16. The apparatus of claim 15 , wherein the multiplexer is further configured to select the one of the first output of the first main amplifier and the second output of the second main amplifier responsive, at least in part, to a control signal which indicates whether a column address input with a column command corresponds to an even or an odd bit line.
17. The apparatus of claim 13 , further comprising:
a third transfer gate coupled between the first sense amplifier and the second I/O line pair; and
a fourth transfer gate coupled between the second sense amplifier and the first I/O line pair.
18. The apparatus of claim 17 , wherein the first and fourth transfer gate are controlled responsive, at least in part, to a control signal and the second and third transfer gate are controlled responsive, at least in part, to an inverted control signal.
19. The apparatus of claim 18 , wherein the first and third transfer gate are controlled responsive, at least in part, to a first address decoded signal and the second and fourth transfer gate are controlled responsive, at least in part, to a second address decoded signal.
20. The apparatus of claim 19 , further comprising a multiplexer coupled to the first main amplifier and the second main amplifier, the multiplexer configured to select at least one of a first output of the first main amplifier and a second output of the second main amplifier responsive to the control signal.