IP Library › Granted Patent US 10,574,274
Granted Patent B2
US 10,574,274 · App. 15/719,753 · Granted Feb 25, 2020

Systems and methods for decoding error correcting codes

Inventors: Yuan-mao Chang (Hsinchu, TW); Jie Chen (Milpitas, CA); Chung-Li Wang (Fremont, CA)
Assignee: Nyquist Semiconductor Limited
H03M13/458H03M13/1108H03M13/1111H03M13/3707H03M13/3723H03M13/3746
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,574,274
App. No.
15/719,753
Filed
Sep 29, 2017
Granted
Feb 25, 2020
Kind
B2
Art Unit
2112
USPC
714/780
Abstract

Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a first decoding on a codeword using a first decoder, determining a number of satisfied check nodes and a number of unsatisfied check nodes for a symbol value of the codeword for a decoding result of the first decoding, generating a soft log-likelihood ratio (LLR) for the symbol value based on the number of satisfied check nodes and the number of unsatisfied check nodes, and performing a second decoding using a second decoder with the soft LLR as an input to the second decoder.

Claims (27)

1. A method, comprising:

performing a first decoding on a codeword using a first decoder;

determining, for a symbol value of the codeword, a number of satisfied check nodes and a number of unsatisfied check nodes for a decoding result of the first decoding;

generating a soft log-likelihood ratio (LLR) for the symbol value by multiplying a scaling factor to a difference between the number of satisfied check nodes and the number of unsatisfied check nodes such that a larger difference generating a larger soft LLR value and a smaller difference generating a smaller soft LLR value; and

performing a second decoding using a second decoder with the soft LLR as an input to the second decoder.

2. The method of claim 1 , wherein the first decoding is a hard decision decoding.

3. The method of claim 1 , wherein the second decoding is a soft decision decoding.

4. The method of claim 1 , wherein the soft LLR for the symbol value is generated according to an equation P=((# S−# U)*Q+1)*D*X, in which P is the soft LLR to be generated, # S is the number of satisfied check nodes, # U is the number of unsatisfied check nodes, Q is the scaling factor, D is the symbol value, X is an original LLR magnitude assigned to the symbol value, and “*” is a multiplication sign.

5. The method of claim 4 , wherein the scaling factor Q and the original LLR magnitude X are selected to satisfy a hardware constraint.

6. The method of claim 1 , wherein the first decoding is an iterative decoding.

7. The method of claim 6 , wherein the soft LLR is generated after a configurable number of iteration(s) of the first decoding.

8. The method of claim 6 , wherein the configurable number is any number between one and a maximum number for iterations.

9. The method of claim 6 , wherein the soft LLR is generated after each iteration of the first decoding.

10. The method of claim 9 , wherein the soft LLR used as the input to the second decoding is the soft LLR generated after any iteration.

11. The method of claim 1 , further comprising adjusting a bit flip threshold during the first decoding.

12. A system, comprising:

a first decoder comprising circuitry configured to perform a first decoding on a codeword;

a soft log-likelihood ratio (LLR) generator comprising circuitry configured to:

determine, for a symbol value of the codeword, a number of satisfied check nodes and a number of unsatisfied check nodes for a decoding result of the first decoding; and

generate a soft log-likelihood ratio (LLR) for the symbol value by multiplying a scaling factor to a difference between the number of satisfied check nodes and the number of unsatisfied check nodes such that a larger difference generating a larger soft LLR value and a smaller difference generating a smaller soft LLR value; and

a second decoder comprising circuitry configured to perform a second decoding using the soft LLR as an input.

13. The system of claim 12 , wherein the first decoder is a hard decision decoder and the second decoder is a soft decision decoder.

14. The system of claim 12 , wherein the soft LLR generator is configured to generate the soft LLR according to an equation P=((# S−# U)*Q+1)*D*X, in which P is the soft LLR to be generated, # S is the number of satisfied check nodes, # U is the number of unsatisfied check nodes, Q is the scaling factor, D is the symbol value, X is an original LLR magnitude assigned to the symbol value, and “*” is a multiplication sign.

15. The system of claim 14 , wherein the scaling factor Q and the original LLR magnitude X are selected to satisfy a hardware constraint.

16. The system of claim 12 , wherein the first decoder is configured to perform an iterative decoding and the soft LLR is generated after a configurable number of iteration(s) of the first decoding, and the configurable number is any number between one and a maximum number for iterations.

17. The system of claim 12 , further comprising a data storage, wherein the codeword is read from the data storage.

18. The system of claim 12 , further comprising a receiver and a demodulator, wherein the codeword is received from a communication channel via the receiver and demodulated by the demodulator.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2020
From: NYQUIST SEMICONDUCTOR LIMITED
To: INNOGRIT TECHNOLOGIES CO., LTD.
Reel/Frame 052333/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2017
From: CHANG, YUAN-MAO; CHEN, JIE; WANG, CHUNG-LI
To: NYQUIST SEMICONDUCTOR LIMITED
Reel/Frame 043737/0339 →
Continuity (1)
Related Publication 20190103885A1 · Apr 4, 2019