Skew sensor with enhanced reliability
A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.
1. A skew control loop circuit for controlling a skew between a plurality of digital signals, comprising:
a skew detector for detecting a phase difference between a plurality of digital signals; signal inputs being received by said skew detector, said signal input being adapted for
inputting said digital signals to said skew detector;
a skew control circuit adapted for controlling an operation of said skew control loop circuit, wherein said skew control circuit is operable in a first operating mode and in a second operating mode; and
an enable input of said skew detector, wherein said enable input is adapted for receiving an enable input signal generated by said skew control circuit, wherein said enable input is adapted to selectively enable or disable a phase detection operation of said skew detector, and wherein said enable input signal is only active during said first operating mode, wherein said skew detector comprises a flip flop.
2. The skew control loop circuit according to claim 1 , wherein said skew detector comprises circuitry operable for preventing a phase detection circuit of said skew detector from entering a metastable state while said first operating mode is disabled.
3. The skew control loop circuit according to claim 2 , wherein said skew control loop circuitry comprises at least one gating circuit operable for gating at least one of said digital signals, wherein said gating circuit is arranged between at least one of said signal inputs and said phase detection circuit.
4. The skew control loop circuit according to claim 1 , wherein said phase difference between said digital signals is measured over a predefined set of cycles.
5. The skew control loop circuit according to claim 4 , wherein said predefined set of cycles comprises 16 cycles.
6. The skew control loop circuit according to claim 4 , wherein said skew detector comprises circuitry operable for preventing a phase detection circuit of said skew detector from entering a metastable state while said first operating mode is disabled, and wherein a determination of being in said metastable state is based on a predefined number of different states in said predefined set of cycles.
7. The skew control loop circuit according to claim 1 , wherein said digital signals are clock signals.
8. A semiconductor device comprising a skew control loop circuit for controlling a skew between a plurality of digital signals, which comprises:
a semiconductor die including a circuit, the circuit comprising:
a skew detector for detecting a phase difference between a plurality of digital signals; signal inputs being received by said skew detector, said signal input being adapted for
inputting said digital signals to said skew detector;
a skew control circuit adapted for controlling an operation of said skew control loop circuit, wherein said skew control circuit is operable in a first operating mode and in a second operating mode; and
an enable input of said skew detector, wherein said enable input is adapted for receiving an enable input signal generated by said skew control circuit, wherein said enable input is adapted to selectively enable or disable a phase detection operation of said skew detector, and wherein said enable input signal is only active during said first operating mode, wherein said skew detector comprises a flip flop.
9. The semiconductor device according to claim 8 , wherein said skew detector comprises circuitry operable for preventing a phase detection circuit of said skew detector from entering a metastable state while said first operating mode is disabled.
10. The semiconductor device according to claim 9 , wherein said skew control loop circuitry comprises at least one gating circuit operable for gating at least one of said digital signals, wherein said gating circuit is arranged between at least one of said signal inputs and said phase detection circuit.
11. The semiconductor device according to claim 8 , wherein said phase difference between said digital signals is measured over a predefined set of cycles, and wherein said skew detector comprises circuitry operable for preventing a phase detection circuit of said skew detector from entering a metastable state while said first operating mode is disabled, and wherein a determination of being in said metastable state is based on a predefined number of alternative states in said predefined set of cycles.