Processor, method, and system for cache partitioning and control for accurate performance monitoring and optimization
Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.
1. A processor comprising:
a cache;
cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses, the cache controller circuitry further to receive a request to access a memory address and responsively determine one of the plurality of cache partitions to which the memory address is assigned, wherein the memory address is assigned to a first cache partition if a portion of the memory address matches a first one of the one or more control addresses and assigned to a second cache partition if the portion of the memory address matches a second one of the one or more control addresses;
cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and
cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.
2. The processor of claim 1 , further comprising a plurality of machine specific registers (MSRs) to store the one or more control addresses, the cache policies, and the partition-specific statistics.
3. The processor of claim 1 , wherein the memory address is assigned to a third cache partition if the portion of the memory address does not match any of the one or more control addresses.
4. The processor of claim 1 , wherein a mask is applied to the memory address to generate the portion of the memory address used for determining a match between the memory address and the one or more control addresses.
5. The processor of claim 4 , wherein the portion of the memory address is used to specify a bit position of the one or more control addresses and wherein the memory address is a match for a first control address if a bit is set at the specified bit position of the first control address and not a match if the bit is not set.
6. The processor of claim 1 , wherein the cache policies comprise cache replacement policies.
7. The processor of claim 1 , wherein the cache policies comprise cache line prefetch policies.
8. The processor of claim 1 , wherein the cache performance monitoring circuitry comprises a plurality of counters, each tracking occurrences of a particular cache event for a specific cache partition.
9. A method comprising:
partitioning, by cache controller circuitry, a processor cache into a plurality of cache partitions based on one or more control addresses;
receiving, by the cache controller circuitry, a request to access a memory address and responsively determining one of the plurality of cache partitions to which the memory address is assigned, wherein the memory address is assigned to a first cache partition if a portion of the memory address matches a first one of the one or more control addresses and assigned to a second cache partition if the portion of the memory address matches a second one of the one or more control addresses;
applying, by cache policy assignment circuitry, different cache policies to different subsets of the plurality of cache partitions; and
tracking, by cache performance monitoring circuitry, cache events for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.
10. The method of claim 9 , wherein the one or more control addresses, the cache policies, and the partition-specific statistics are stored in a plurality of machine specific registers (MSRs).
11. The method of claim 9 , wherein the memory address is assigned to a third cache partition if the portion of the memory address does not match any of the one or more control addresses.
12. The method of claim 9 , further comprising applying a mask to the memory address to generate the portion of the memory address used for determining a match between the memory address and the one or more control addresses.
13. The method of claim 12 , wherein the portion of the memory address is used to specify a bit position of the one or more control addresses and wherein the memory address is a match for a first control address if a bit is set at the specified bit position of the first control address and not a match if the bit is not set.
14. The method of claim 9 , wherein the cache policies comprise cache replacement policies.
15. The method of claim 9 , wherein the cache policies comprise cache line prefetch policies.
16. The method of claim 9 , wherein the cache performance monitoring circuitry comprises a plurality of counters, each tracking occurrences of a particular cache event for a specific cache partition.
17. A system comprising:
a memory;
a processor comprising:
a plurality of cores;
a cache shared by the plurality of cores;
cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses, the cache controller circuitry further to receive a request to access a memory address and responsively determine one of the plurality of cache partitions to which the memory address is assigned, wherein the memory address is assigned to a first cache partition if a portion of the memory address matches a first one of the one or more control addresses and assigned to a second cache partition if the portion of the memory address matches a second one of the one or more control addresses;
cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and
cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.
18. The system of claim 17 , further comprising a plurality of machine specific registers (MSRs) to store the control address, the cache policies, and the partition-specific statistics.
19. The system of claim 17 , wherein the memory address is assigned to a third cache partition if the portion of the memory address does not match any of the one or more control addresses.
20. The system of claim 17 , wherein a mask is applied to the memory address to generate the portion of the memory address used for determining a match between the memory address and the one or more control addresses.
21. The system of claim 20 , wherein the portion of the memory address is used to specify a bit position of the one or more control addresses and wherein the memory address is a match for a first control address if a bit is set at the specified bit position of the first control address and not a match if the bit is not set.
22. The system of claim 17 , wherein the cache performance monitoring circuitry comprises a plurality of counters, each tracking occurrences of a particular cache event for a specific cache partition.