Automated test generation for structural coverage for temporal logic falsification of cyber-physical systems

1. A method for model verification, comprising:

obtaining, by a processor, a model for a system;

identifying, by the processor, at least one block within the model that has a branching structure;

identifying, by the processor, at least one model variable affecting a switching condition of the identified at least one block;

generating, by the processor, an extended finite state machine modeling a switching behavior of the identified at least one block by using the at least one model variable;

combining, by the processor, at least one output variable of the extended finite state machine with at least one of a first output port and a second output port of the system included in the model; and

performing, by the processor, model verification and coverage of the model that utilizes outputs from the first output port and the second output port to verify the model,

wherein performing the model verification comprises performing coverage analysis by collecting coverage statistics for at least the first output port, and performing coverage guided falsification comprises:

determining if a falsification process executed as part of the model verification process has terminated successfully or unsuccessfully; and

modifying the model verification process to perform a coverage-guided falsification process in which preference is first given to combinations of modes of the model that were evaluated as part of the model verification process and had the lowest coverage statistics based on the collected coverage statistics, wherein performing a coverage-guided falsification process comprises minimizing a robustness of the model and guiding the model verification process to modes that had the lowest coverage statistics.

2. The method of claim 1 , further comprising generating, for the identified at least one block, a third output port, wherein model verification of the model utilizes the first, second, and third output ports to perform the model verification.

3. The method of claim 1 , further comprising flattening the obtained model to produce a directed graph that includes block connectivity information.

4. The method of claim 3 , further comprising annotating the model, wherein the annotated model is analyzed/processed to identify the at least one block that has a branching structure.

5. The method of claim 1 , wherein the model can contain one or more of hardware in the loop or software in the loop components.

6. A method for code verification, comprising:

obtaining, by a processor, embedded code;

identifying, by the processor, at least one block within the embedded code that has a branching structure;

generating, by the processor, a first output variable based on an extracted extended finite state machine for the identified at least one block;

combining, by the processor, the first output variable generated based on the extracted extended finite state machine with at least a second output variable of the system included in the embedded code; and

performing, by the processor, coverage analysis and coverage guided falsification of the embedded code that utilizes the first and second output variable to verify the embedded code,

wherein performing coverage guided falsification comprises:

determining if a falsification process executed as part of the model verification process has terminated successfully or unsuccessfully;

modifying the model verification process to perform a coverage-guided falsification process in which preference is first given to combinations of modes of the model that were evaluated as part of the model verification process and had the lowest coverage statistics based on the collected coverage statistics; and

minimizing a robustness of the model and guiding the model verification process having the lowest coverage statistics.