Technologies for secure encrypted external memory for field-programmable gate arrays (FPGAS)

1. A computing device for data security, the computing device comprising:

an external memory device; and

a field-programmable gate array (FPGA) coupled to the external memory device, wherein the FPGA is to:

execute a first user kernel of the FPGA, wherein the first user kernel is identified by a first index;

store a first symmetric encryption key associated with the first index, wherein the first symmetric encryption key is not accessible by user kernels of the FPGA;

read encrypted input data from the external memory device coupled to the FPGA;

decrypt the encrypted input data with the first symmetric encryption key to generate plain input text data in response to a reading of the encrypted input data;

forward the plain text input data to the first user kernel in response to decryption of the encrypted input data;

receive plain text output data from the first user kernel;

encrypt the plain text output data with the first symmetric encryption key to generate encrypted output data in response to receipt of the plain text output data; and

write the encrypted output data to the external memory device in response to encryption of the plain text output data.

2. The computing device of claim 1 , wherein the FGPA is further to write the first index in the external memory device in response to the encryption of the plain text output data.

3. The computing device of claim 1 , further comprising:

one or more processors; and

one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the computing device to program the FGPA with the first user kernel;

wherein to execute the first user kernel comprises to execute the first user kernel in response to programming of the FGPA.

4. The computing device of claim 1 , further comprising:

one or more processors; and

one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the computing device to securely provision the FPGA with the first symmetric encryption key at the first index;

wherein to store the first symmetric encryption key comprises to store the first symmetric encryption key in response to provisioning of the FGPA with the first symmetric encryption key.

5. The computing device of claim 4 , wherein to securely provision the FGPA with the first symmetric encryption key comprises to perform a network key exchange with the FPGA using an FPGA device key that is unique to the FPGA.

6. The computing device of claim 4 , wherein to securely provision the FGPA with the first symmetric encryption key comprises to perform a PCI express data transfer with the FPGA.

7. The computing device of claim 4 , wherein the FPGA is further to return the first index in response to the provisioning of the FGPA with the first symmetric encryption key.

8. The computing device of claim 1 , wherein:

to store the first symmetric encryption key associated with the first index comprises to store the first symmetric encryption key with a secure key store programmed block of the FPGA; and

to perform the cryptographic operation comprises to perform the cryptographic operation with a micro encryption engine programmed block of the FPGA.

9. The computing device of claim 1 , wherein the FPGA is further to:

retrieve the first symmetric encryption key with the first index;

wherein to perform the cryptographic operation comprises to perform the cryptographic operation in response to providing of the first symmetric encryption key.

10. The computing device of claim 1 , wherein the first user kernel comprises a programmed user block of the FPGA.

11. The computing device of claim 1 , wherein to store the first symmetric encryption key comprises to store the first symmetric encryption key in a write-only key store of the FPGA.

12. The computing device of claim 1 , wherein the FPGA is further to:

execute a second user kernel of the FPGA, wherein the second user kernel is identified by a second index; and

store a second symmetric encryption key associated with the second index, wherein the second symmetric encryption key is not accessible by the first user kernel of the FPGA.

13. One or more non-transitory computer-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a computing device to:

execute a first user kernel of a field-programmable gate array (FPGA) of the computing device, wherein the first user kernel is identified by a first index;

store, by the FPGA, a first symmetric encryption key associated with the first index, wherein the first symmetric encryption key is not accessible by user kernels executed by the FPGA;

read, by the FPGA, encrypted input data from the external memory device;

decrypt, by the FPGA, the encrypted input data with the first symmetric encryption key to generate plain text input data in response to reading the encrypted input data;

forward, by the FPGA, the plain text input data to the first user kernel in response to decrypting the encrypted input data;

receive, by the FPGA, plain text output data from the first user kernel;

encrypt, by the FPGA, the plain text output data with the first symmetric encryption key to generate encrypted output data in response to receiving the plain text output data; and

write, by the FGPA, the encrypted output data to the external memory device in response to encrypting the plain text output data.

14. The one or more non-transitory computer-readable storage media of claim 13 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the computing device to write, by the FPGA, the first index in the external memory device in response to encrypting the plain text output data.

15. The one or more non-transitory computer-readable storage media of claim 13 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the computing device to:

program, by the computing device, the FGPA with the first user kernel;

wherein to execute the first user kernel comprises to execute the first user kernel in response to programming the FGPA.

16. The one or more non-transitory computer-readable storage media of claim 13 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the computing device to:

securely provision the FPGA with the first symmetric encryption key at the first index;

wherein to store the first symmetric encryption key comprises to store the first symmetric encryption key in response to securely provisioning the FGPA with the first symmetric encryption key.

17. The one or more non-transitory computer-readable storage media of claim 16 , wherein to securely provision the FGPA with the first symmetric encryption key comprises to perform a network key exchange with the FPGA using an FPGA device key that is unique to the FPGA.

18. The one or more non-transitory computer-readable storage media of claim 16 , wherein to securely provision the FGPA with the first symmetric encryption key comprises to perform a PCI express data transfer with the FPGA.

19. The one or more non-transitory computer-readable storage media of claim 16 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the computing device to return, by the FPGA, the first index in response to provisioning the FGPA with the first symmetric encryption key.

20. The one or more non-transitory computer-readable storage media of claim 13 , wherein:

to store the first symmetric encryption key associated with the first index comprises to store the first symmetric encryption key with a secure key store programmed block of the FPGA; and

to perform the cryptographic operation comprises to perform the cryptographic operation with a micro encryption engine programmed block of the FPGA.

21. The one or more non-transitory computer-readable storage media of claim 13 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the computing device to:

retrieve, by the FPGA, the first symmetric encryption key with the first index;

wherein to perform the cryptographic operation comprises to perform the cryptographic operation in response to retrieving the first symmetric encryption key.

22. The one or more non-transitory computer-readable storage media of claim 13 , wherein the first user kernel comprises a programmed user block of the FPGA.

23. The one or more non-transitory computer-readable storage media of claim 13 , wherein to store the first symmetric encryption key comprises to store the first symmetric encryption key in a write-only key store of the FPGA.

24. The one or more non-transitory computer-readable storage media of claim 13 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the computing device to:

execute, by a computing device, a second user kernel of the FPGA, wherein the second user kernel is identified by a second index; and

store, by the FPGA, a second symmetric encryption key associated with the second index, wherein the second symmetric encryption key is not accessible by the first user kernel of the FPGA.

25. A computing device for data security, the computing device comprising:

circuitry for executing a first user kernel of a field-programmable gate array (FPGA) of the computing device, wherein the first user kernel is identified by a first index;

means for storing, by the FPGA, a first symmetric encryption key associated with the first index, wherein the first symmetric encryption key is not accessible by user kernels executed by the FPGA;

means for reading, by the FPGA, encrypted input data from the external memory device;

means for decrypting, by the FPGA, the encrypted input data with the first symmetric encryption key to generate plain text input data in response to reading the encrypted input data;

means for forwarding, by the FPGA, the plain text input data to the first user kernel in response to decrypting the encrypted input data;

means for receiving, by the FPGA, plain text output data from the first user kernel;

means for encrypting, by the FPGA, the plain text output data with the first symmetric encryption key to generate encrypted output data in response to receiving the plain text output data; and

means for writing, by the FGPA, the encrypted output data to the external memory device in response to encrypting the plain text output data.

26. A method for data security, the method comprising:

executing, by a computing device, a first user kernel of a field-programmable gate array (FPGA) of the computing device, wherein the first user kernel is identified by a first index;

storing, by the FPGA, a first symmetric encryption key associated with the first index, wherein the first symmetric encryption key is not accessible by user kernels executed by the FPGA;

reading, by the FPGA, encrypted input data from the external memory device;

decrypting, by the FPGA, the encrypted input data with the first symmetric encryption key to generate plain text input data in response to reading the encrypted input data;

forwarding, by the FPGA, the plain text input data to the first user kernel in response to decrypting the encrypted input data;

receiving, by the FPGA, plain text output data from the first user kernel;

encrypting, by the FPGA, the plain text output data with the first symmetric encryption key to generate encrypted output data in response to receiving the plain text output data; and

writing, by the FGPA, the encrypted output data to the external memory device in response to encrypting the plain text output data.

27. The method of claim 26 , further comprising:

programming, by the computing device, the FGPA with the first user kernel;

wherein executing the first user kernel comprises executing the first user kernel in response to programming the FGPA.

28. The method of claim 26 , further comprising:

securely provisioning, by the computing device, the FPGA with the first symmetric encryption key at the first index;

wherein storing the first symmetric encryption key comprises storing the first symmetric encryption key in response to securely provisioning the FGPA with the first symmetric encryption key.