FinFETs and methods for forming the same
A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.
1. A device comprising:
a semiconductor fin comprising:
an inner region; and
a germanium-doped layer on a top surface and sidewall surfaces of the inner region, wherein the germanium-doped layer has a higher germanium concentration than the inner region;
a gate stack comprising:
a gate dielectric over the germanium-doped layer; and
a gate electrode over the gate dielectric;
a source region connected to a first end of the semiconductor fin;
a drain region connected to a second end of the semiconductor fin opposite the first end, wherein the germanium-doped layer comprises an end facing the source region, and the end is substantially vertically aligned to a sidewall of the gate stack; and
a shallow trench isolation region having opposite portions on opposite sides of the semiconductor fin, wherein the germanium-doped layer comprises:
a sidewall portion having an inner sidewall surface contacting one of the sidewall surfaces of the inner region; and
an outer sidewall surface vertically aligned to a sidewall of the shallow trench isolation region.
2. The device of claim 1 , wherein the germanium-doped layer is a substantially conformal layer.
3. The device of claim 1 , wherein the source region and the drain region are substantially free from germanium.
4. The device of claim 1 , wherein the inner region is substantially free from germanium.
5. The device of claim 1 , wherein the end of the germanium-doped layer has a sidewall contacting a portion of the source region, and the portion of the source region has a first silicon percentage and a first germanium percent different from a second silicon percentage and a second germanium percentage of the germanium-doped layer.
6. The device of claim 1 further comprising a semiconductor strip between the opposite portions of the shallow trench isolation region, wherein the inner sidewall surface overlaps the semiconductor strip.
7. The device of claim 1 , wherein an entirety of the germanium-doped layer is overlapped by the gate dielectric.
8. The device of claim 1 , wherein the gate dielectric contacts the germanium-doped layer.
9. A device comprising:
a semiconductor substrate;
an isolation region extending into the semiconductor substrate;
a semiconductor strip between opposite portions of the isolation region, wherein opposite edges of the semiconductor strip are in physical contact with edges of the opposite portions of the isolation region; and
a Fin Field-Effect Transistor (FinFET) comprising:
a semiconductor fin comprising:
a silicon inner region substantially free from germanium; and
a germanium-doped layer comprising:
a top portion overlapping the silicon inner region; and
a sidewall portion on a sidewall of the silicon inner region, wherein a bottom end of the sidewall portion is substantially at a same level as a top surface of the isolation region, and the germanium-doped layer has an outer edge vertically aligned to an interface between the semiconductor strip and the isolation region;
a gate dielectric contacting the germanium-doped layer; and
a gate electrode over the gate dielectric.
10. The device of claim 9 , wherein the top portion and the sidewall portion of the germanium-doped layer have substantially a same thickness.
11. The device of claim 9 further comprising:
a source region connected to a first end of the germanium-doped layer and the silicon inner region, wherein a portion of the source region has a sidewall contacting the first end to form an interface, and the portion of the source region has a different germanium percentage than a germanium percentage of the germanium-doped layer; and
a drain region connected to a second end of the germanium-doped layer and the silicon inner region, wherein the second end is opposite to the first end.
12. The device of claim 11 , wherein the interface is vertically aligned to a sidewall of the gate dielectric.
13. The device of claim 9 , wherein the germanium-doped layer has a germanium doping concentration between about 4E20/cm 3 and about 5E21/cm 3 .
14. The device of claim 9 , wherein the gate dielectric and the gate electrode in combination form a gate stack, and opposite sidewalls of the gate stack are flush with opposite ends of the germanium-doped layer.
15. A device comprising:
a semiconductor substrate;
an isolation region extending into the semiconductor substrate, wherein a portion of the semiconductor substrate is located between opposite portions of the isolation region to form a semiconductor strip, and the opposite portions of the isolation region have a first horizontal distance; and
a Fin Field-Effect Transistor (FinFET), wherein the FinFET is an n-type FinFET comprising:
a semiconductor fin comprising:
a silicon fin higher than the isolation region and overlapping the semiconductor strip; and
a germanium-doped layer comprising a first sidewall portion and a second sidewall portion contacting opposite sidewalls of the silicon fin to form a first vertical interface and a second vertical interface, respectively, and a second horizontal distance between the first vertical interface and the second vertical interface is smaller than the first horizontal distance, wherein the germanium-doped layer has a higher germanium concentration than the silicon fin;
a gate dielectric comprising portions on sidewalls of the germanium-doped layer; and
a gate electrode over the gate dielectric.
16. The device of claim 15 , wherein a bottom surface of the germanium-doped layer is at substantially a same level as a top surface of the isolation region.
17. The device of claim 16 , wherein the germanium-doped layer is limited in a region directly under the gate dielectric.
18. The device of claim 15 further comprising:
a source region and a drain region, wherein opposite ends of the silicon fin and the germanium-doped layer are in contact with the source region and the drain region.
19. The device of claim 18 , wherein the source region and the drain region are free from germanium.
20. The device of claim 15 , wherein the germanium-doped layer further comprises a top portion overlapping the silicon fin.