Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
wherein said buried layer region is commonly connected to at least two of said memory cells.
2. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a phase change material.
3. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a metal-oxide-metal system.
4. The semiconductor memory array of claim 1 , wherein said floating body is configured to store a state of said bipolar device.
5. The semiconductor memory array of claim 1 , wherein said nonvolatile memory stores said data stored in said bipolar device upon loss of power to said cell, and wherein said cell is configured to perform a shadowing process during which said data in said bipolar device is loaded into and stored in said nonvolatile memory.
6. The semiconductor memory array of claim 1 , wherein said bipolar device is fabricated on a silicon on insulator substrate.
7. The semiconductor memory array of claim 1 , wherein said bipolar device is formed in a fin.
8. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a bottom electrode, a resistance change material and a top electrode.
9. The semiconductor memory array of claim 1 , wherein said data stored in said bipolar device is transferred to said nonvolatile memory upon loss of power to said memory array.
10. The semiconductor memory array of claim 1 , wherein said data stored in said bipolar device is transferred to said nonvolatile memory upon receiving an instruction to back up said data stored in said bipolar device.
11. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
a buried layer terminal electrically connected to said buried layer region;
wherein when a first memory cell of said plurality of semiconductor memory cells is in a first charge level and a second memory cell of said plurality of semiconductor memory cells is in a second charge level, upon said transfer of data, said first memory cell stores a first nonvolatile memory state and second memory cell stores a second nonvolatile memory state, said first and second nonvolatile memory states being non-algorithmically determined by said first and second charge levels of said first and second memory cells, respectively.
12. The semiconductor memory array of claim 11 , wherein said resistance change element comprises a phase change material.
13. The semiconductor memory array of claim 11 , wherein said resistance change element comprises a metal-oxide-metal system.
14. The semiconductor memory array of claim 11 , wherein said floating body is configured to store a state of said bipolar device.
15. The semiconductor memory array of claim 11 , wherein said nonvolatile memory stores said data stored in said bipolar device upon loss of power to said cell, and wherein said cell is configured to perform a shadowing process during which said data in said bipolar device is loaded into and stored in said nonvolatile memory.
16. The semiconductor memory array of claim 11 , wherein said bipolar device is fabricated on a silicon on insulator substrate.
17. The semiconductor memory array of claim 11 , wherein said bipolar device is formed in a fin.
18. The semiconductor memory array of claim 11 , wherein said resistance change element comprises a bottom electrode, a resistance change material and a top electrode.
19. The semiconductor memory array of claim 11 , wherein said data stored in said bipolar device is transferred to said nonvolatile memory upon loss of power to said memory array.
20. The semiconductor memory array of claim 11 , wherein said data stored in said bipolar device is transferred to said nonvolatile memory upon receiving an instruction to back up said data stored in said bipolar device.