Granted Patent B2

US 12,665,024 · App. 18/538,220 · Granted Jun 23, 2026

Inventor: Yuniarto Widjaja (Cupertino, CA)

Assignee: Zeno Semiconductor, Inc.

G11C14/0018G11C11/404G11C11/565G11C16/06H10B12/00H10B12/20H10B41/30H10B41/35H10D30/0411H10D30/0413H10D30/68H10D30/681H10D30/6892H10D30/711H10D62/115H10D64/661G11C16/0416G11C16/0433G11C2211/4016

Abstract

Claims (67)

1 . An integrated circuit comprising:

an array of semiconductor memory cells, the array comprising:

a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:

a transistor comprising a source region, a floating body region, a drain region, and a gate,

a first bipolar device having a first floating base region, a first collector, and a first emitter, and

a second bipolar device having a second floating base region, a second collector, and a second emitter,

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein a state of each of said at least two of said memory cells is maintained through a back-bias applied to said first and second collectors,

wherein said first and second collectors are commonly connected to said at least two of said memory cells;

wherein said transistor is usable to access said memory cells; and

a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors;

a control circuit configured to apply said back-bias to said first and second collectors; and

a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.

2 . The integrated circuit of claim 1 ,

wherein said first and second floating base regions have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

wherein said first and second emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

wherein said conductivity type of first and second collectors and said region is said second conductivity type.

3 . The integrated circuit of claim 1 , wherein said back-bias applied to said first and second collectors is a constant voltage bias.

4 . The integrated circuit of claim 1 , wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.

5 . The integrated circuit of claim 1 , wherein said gate region is located above said first and second floating base regions.

6 . The integrated circuit of claim 1 , wherein a maximum potential that can be stored in said first and second floating base regions is increased by said applying back bias to said first and second collectors, resulting in a relatively larger memory window.

7 . The integrated circuit of claim 1 , comprising fin structures extending from a substrate.

8 . An integrated circuit comprising:

an array of semiconductor memory cells, the array comprising:

a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first collector, and a first emitter, and

a second bipolar device having a second floating base region, a second collector, and a second emitter;

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein application of back-bias to said first and second collectors results in at least two stable floating base region charge levels,

wherein said first and second collectors are commonly connected to at least two of said memory cells;

wherein said transistor is usable to access said memory cell; and

a region extending from and electrically connected to said first and second collectors, wherein said region has a conductivity type selected from a p-type conductivity type and an n-type conductivity type that is the same as a conductivity type of said first and second collectors;

a control circuit configured to apply said back-bias to said first and second collectors; and

a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.

9 . The integrated circuit of claim 8 ,

wherein said first and second floating base regions have a first conductivity type selected from said p-type conductivity type and said n-type conductivity type;

wherein each said first and second emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

wherein said conductivity type of said first and second collectors and said region is said second conductivity type.

10 . The integrated circuit of claim 8 , wherein said back-bias applied to said first and second collectors is a constant voltage bias.

11 . The integrated circuit of claim 8 , wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.

12 . The integrated circuit of claim 8 , wherein said gate region is located above said first and second floating base regions.

13 . The integrated circuit of claim 8 , wherein a maximum potential that can be stored in said floating base regions is increased by said applying back bias to said first and second collectors, resulting in a relatively larger memory window.

14 . The integrated circuit of claim 8 , comprising fin structures extending from a substrate.

15 . An integrated circuit comprising:

an array of semiconductor memory cells, the array comprising:

a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said plurality of semiconductor memory cells includes:

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first collector, and a first emitter; and

a second bipolar device having a second floating base region, a second collector, and a second emitter;

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein said transistor is usable to access said memory cell; and

wherein states of said semiconductor memory cells are maintained upon repeated read operations;

a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors;

a control circuit configured to apply back-bias to said first and second collectors; and

a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.

16 . The integrated circuit of claim 15 , wherein at least one of said first bipolar device or said second bipolar device maintains the state of said semiconductor memory cell, and

wherein said first and second collectors are commonly connected to at least two of said semiconductor memory cells.

17 . The integrated circuit of claim 15 , wherein said floating base regions have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said collectors and said region have said second conductivity type.

18 . The integrated circuit of claim 15 , wherein said back-bias is applied to said first and second collectors via a voltage bias applied as a constant voltage bias, a periodic pulse of voltage, or a serial combination of constant voltage bias and periodic pulse of voltage.

19 . The integrated circuit of claim 15 , wherein a maximum potential that can be stored in said floating base regions is increased by applying said back bias to said first and second collectors, resulting in a relatively larger memory window.

20 . The integrated circuit of claim 15 , comprising a fin structure extending from a substrate.

Assignments (1)

Continuity (21)

References Cited (386)