Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
a substrate;
a transistor comprising a source region, a first floating body region, a drain region, and a gate;
a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein:
one of said cathode region and said anode region comprises said substrate,
a state of said memory cell is stored in said first floating body region,
said first floating body region and said second floating body region are common,
said silicon controlled rectifier device maintains a state of said memory cell, and
said transistor is usable to access said memory cell; and
a nonvolatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer to said nonvolatile memory;
wherein said buried layer region is commonly connected to at least two of said memory cells.
2. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a bottom electrode, a resistance change material and a top electrode.
3. The semiconductor memory array of claim 1 , wherein said resistance change element is electrically connected to one of said source region and said drain region through a conductive element.
4. The semiconductor memory array of claim 1 , wherein said resistance change element is connected to an address line.
5. The semiconductor memory array of claim 2 , wherein said resistance change element is connected to an address line through said top electrode.
6. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a phase change material.
7. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a metal-oxide-metal system.
8. The semiconductor memory array of claim 1 , wherein said transistor is formed in a fin.
9. The semiconductor memory array of claim 1 , wherein said state of said memory cell stored in said first floating body region is transferred to said nonvolatile memory upon loss of power to said memory array.
10. The semiconductor memory array of claim 1 , wherein said state of said memory cell stored in said first floating body region is transferred to said nonvolatile memory upon receiving an instruction to back up said memory array.
11. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
a substrate;
a transistor comprising a source region, a first floating body region, a drain region, and a gate;
a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein:
one of said cathode region and said anode region comprises said substrate,
a state of said memory cell is stored in said first floating body region, said first floating body region and said second floating body region are common,
said silicon controlled rectifier device maintains a state of said memory cell, and
said transistor is usable to access said memory cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer to said nonvolatile memory;
wherein said buried layer region is commonly connected to at least two of said memory cells; and
a control circuit configured to perform transfer of said data stored in said first floating body region to said nonvolatile memory.
12. The integrated circuit of claim 11 , wherein said resistance change element comprises a bottom electrode, a resistance change material and a top electrode.
13. The integrated circuit of claim 11 , wherein said resistance change element is electrically connected to one of said source region and said drain region through a conductive element.
14. The integrated circuit of claim 11 , wherein said resistance change element is connected to an address line.
15. The integrated circuit of claim 12 , wherein said resistance change element is connected to an address line through said top electrode.
16. The integrated circuit of claim 11 , wherein said resistance change element comprises a phase change material.
17. The integrated circuit of claim 11 , wherein said resistance change element comprises a metal-oxide-metal system.
18. The integrated circuit of claim 11 , wherein said transistor is formed in a fin.
19. The integrated circuit of claim 11 , wherein said state of said memory cell stored in said first floating body region is transferred to said nonvolatile memory upon loss of power to said memory array.
20. The integrated circuit of claim 11 , wherein said state of said memory cell stored in said first floating body region is transferred to said nonvolatile memory upon receiving an instruction to back up said memory array.