Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
1. An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising:
a substrate;
a floating body region exposed at a surface of said substrate and configured to store volatile memory;
a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate;
a select gate positioned adjacent said substrate and said floating gate;
wherein said floating gate is configured to receive transfer of data stored by the volatile memory; and
a control circuit configured to perform operations on said memory array.
2. The integrated circuit of claim 1 , wherein each said semiconductor memory cell further comprises:
first and second regions each exposed at said surface at locations other than where said floating body region is exposed;
wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.
3. The integrated circuit of claim 2 , wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to a coupling of the other of said first and second regions to said floating gate.
4. The integrated circuit of claim 1 , wherein each of said semiconductor memory cells further comprises a buried layer buried in a bottom portion of said substrate, wherein said buried layer has a conductivity type that is different from a conductivity type of said floating body region.
5. The integrated circuit of claim 4 , wherein said floating body region is bounded by said surface, said first and second regions and said buried layer.
6. The integrated circuit of claim 5 , further comprising insulating layers bounding side surfaces of said substrate.
7. The integrated circuit of claim 1 , wherein each of said semiconductor memory cells further comprises a buried insulator layer buried in a bottom portion of said substrate.
8. The integrated circuit of claim 7 , wherein said floating body is bounded by said surface, said first and second regions and said buried insulator layer.
9. An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising:
a substrate;
a floating body region configured to store volatile memory;
a buried layer buried in a bottom portion of said substrate, said buried layer having a conductivity type different from a conductivity type of said floating body region;
a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate;
a select gate positioned adjacent said substrate and said floating gate;
wherein applying a bias to said buried layer results in at least two stable floating body region charge levels;
wherein said buried layer is commonly connected to at least two of said memory cells; and
a control circuit configured to perform operations on said memory array.
10. The integrated circuit of claim 9 , wherein said buried layer comprises a “p′” type conductivity type and said floating body region comprises an “n” type conductivity type.
11. The integrated circuit of claim 9 , wherein said buried layer comprises an “n” type conductivity type and said floating body comprises a “p” type conductivity type.
12. The integrated circuit of claim 9 , wherein each said semiconductor memory cell further comprises insulating layers bounding side surfaces of said substrate.
13. The integrated circuit of claim 9 , wherein operations can be performed on data stored as said volatile memory regardless of a state of data stored as said non-volatile memory.
14. The integrated circuit of claim 13 , wherein said operations include read, write, hold, reset and shadow.
15. The integrated circuit of claim 9 , wherein operations can be performed on data stored as said non-volatile memory regardless of a state of data stored as said volatile memory.