Memory cells, memory cell arrays, methods of using and methods of making
A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
1. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and
a nonvolatile memory comprising a resistance change element configured to store data stored in said floating body upon transfer thereto;
wherein said nonvolatile memory is configured to restore said data to said floating body by a restore operation;
wherein said restore operation is performable to said at least two of said memory cells in parallel; and
said integrated circuit being configured to perform said restore operation.
2. The integrated circuit of claim 1 , wherein said resistance change element comprises a phase change material.
3. The integrated circuit of claim 1 , wherein said resistance change element comprises a metal-oxide-metal system.
4. The integrated circuit of claim 1 , wherein said nonvolatile memory is configured to store said data stored in said floating body upon receiving an instruction to back up said data stored in said floating body.
5. The integrated circuit of claim 1 , wherein said nonvolatile memory is configured to store said data stored in said floating body upon a loss of power to said array, wherein said array is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory.
6. The integrated circuit of claim 5 , wherein said loss of power to said array is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.
7. The integrated circuit of claim 5 , wherein, upon restoration of power to said array, said data in said nonvolatile memory is loaded into said floating body and stored therein.
8. The integrated circuit of claim 7 , wherein said array is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.
9. The integrated circuit of claim 1 , wherein said capacitorless transistor is formed in a fin.
10. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a capacitorless transistor configured to store data as charge therein when power is applied to said memory cell; and
a nonvolatile memory comprising a resistance change element configured to store data stored in said capacitorless transistor upon transfer thereto;
wherein said nonvolatile memory is configured to restore said data to said capacitorless transistor;
wherein charge flow into said capacitorless transistor upon execution of a restore operation to said memory cell depends on charge stored in said resistance change element; and
a control circuit configured to perform said restore operation.
11. The integrated circuit of claim 10 , wherein said resistance change element comprises a phase change material.
12. The integrated circuit of claim 10 , wherein said resistance change element comprises a metal-oxide-metal system.
13. The integrated circuit of claim 10 , wherein said capacitorless transistor comprises a floating body region configured to store a state of said capacitorless transistor.
14. The integrated circuit of claim 13 , further comprising:
a buried layer region in electrical contact with said floating body region, located below said floating body region.
15. The integrated circuit of claim 10 , wherein said nonvolatile memory is configured to store said data stored in said capacitorless transistor upon receiving an instruction to back up said data stored in said capacitorless transistor.
16. The integrated circuit of claim 10 , wherein said nonvolatile memory is configured to store said data stored in said capacitorless transistor upon a loss of power to said memory array, wherein said memory array is configured to perform a shadowing process wherein said data in said capacitorless transistor is loaded into and stored in said nonvolatile memory.
17. The integrated circuit of claim 16 , wherein said loss of power to said memory array is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.
18. The integrated circuit of claim 16 , wherein, upon restoration of power to said memory array, said data in said nonvolatile memory is loaded into said capacitorless transistor and stored therein.
19. The integrated circuit of claim 18 , wherein said memory array is configured to reset said nonvolatile memory to an initial state after loading said data into said capacitorless transistor upon said restoration of power.
20. The integrated circuit of claim 10 , wherein said capacitorless transistor is formed in a fin.
21. The integrated circuit of claim 10 , wherein said data stored in said capacitorless transistor determines a current flowing to said nonvolatile memory.