Nonvolatile memory structure and fabrication method thereof
According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
1. A single-poly nonvolatile memory (NVM) cell, comprising:
a select transistor on a first well of a semiconductor substrate, wherein the select transistor comprises a select gate, a first gate oxide layer between the select gate and the semiconductor substrate, a first source/drain doping region in the first well, and a second source/drain doping region spaced apart from the first source/drain doping region;
a floating gate transistor on the first well serially connected to the select transistor, wherein the PMOS floating gate transistor comprises a floating gate, a second gate oxide layer between the floating gate and the semiconductor substrate, the second source/drain doping region commonly shared by the select transistor, and a third source/drain doping region spaced apart from the second source/drain doping region;
a first salicide layer on the first source/drain doping region;
a protector oxide layer covering and being in direct contact with the floating gate;
a contact etch stop layer on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer;
a first sidewall spacer provided on either sidewall of the select gate;
a second sidewall spacer provided on either sidewall of the floating gate; and
a second salicide layer on the second source/drain doping region, wherein the second salicide layer is contiguous with an edge of a bottom of the first sidewall spacer, but is kept a predetermined distance from an edge of a bottom of the second sidewall spacer.
2. The single-poly NVM cell according to claim 1 further comprising a third salicide layer on the third source/drain doping region, wherein the third salicide layer is kept a predetermined distance from an edge of a bottom of the second sidewall spacer.
3. The single-poly NVM cell according to claim 2 further comprising a fourth salicide layer on a top surface of the select gate.
4. The single-poly NVM cell according to claim 1 wherein no silicide layer is formed on a top surface of the floating gate.
5. The single-poly NVM cell according to claim 1 further comprising an inter-layer dielectric layer on the contact etch stop layer.
6. The single-poly NVM cell according to claim 5 further comprising a source line contact and a bit line contact in the inter-layer dielectric layer to electrically connected to the first source/drain doping region and the third source/drain doping region respectively.
7. The single-poly NVM cell according to claim 1 wherein the protector oxide layer is a silicon oxide layer.
8. The single-poly NVM cell according to claim 1 wherein the protector oxide layer covers and is in direct contact with a top surface of the floating gate, surfaces of the second sidewall spacers, only a portion of the second source/drain doping region, and only a portion of the third source/drain doping region.
9. The single-poly NVM cell according to claim 2 wherein the third salicide layer is formed only on the surface area of the third source/drain doping region not covered by the protector oxide layer.
10. The single-poly NVM cell according to claim 1 wherein the second gate oxide layer is thicker than the first gate oxide layer.